74LV259
8-bit addressable latch
Rev. 03 — 2 January 2008
Product data sheet
1. General description
The 74LV259 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC259 and 74HCT259. The 74LV259 is a high-speed 8-bit addressable latch
designed for general purpose storage applications in digital systems. The 74LV259 is
multifunctional device capable of storing single-line data in eight addressable latches, and
also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are
available. The 74LV259 also incorporates an active LOW common reset (MR) for resetting
all latches, as well as, an active LOW enable input (LE).
The 74LV259 has four modes of operation as shown in the mode select table. In the
addressable latch mode, data on the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all non-addressed latches remaining in their
previous states. In the memory mode, all latches remain in their previous states and are
unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode,
the addressed output follows the state of the (D) input with all other outputs in the LOW
state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2)
and data (D) input. When operating the 74LV259 as an address latch, changing more than
one bit of address could impose a transient-wrong address. Therefore, this should only be
done while in the memory mode.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
s
s
NXP Semiconductors
74LV259
8-bit addressable latch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV259N
74LV259D
74LV259DB
74LV259PW
74LV259BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
4. Functional diagram
15
13
G8
Z9
14
DX
0
9,10D
1 C10
8R
4
LE
13
D
Q0
Q1
Q2
Q3
4
5
6
7
9
10
11
12
1
2
3
14
0
G
2
0
7
1
2
3
4
5
6
7
5
6
7
9
10
11
12
001aah119
1
2
3
A0
A1
A2
MR
15
Q4
Q5
Q6
Q7
001aah118
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LV259_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 January 2008
2 of 19
NXP Semiconductors
74LV259
8-bit addressable latch
Q0
Q1
1
2
3
A0
A1
A2
8 LATCHES
1 OF 8
DECODER
Q2
Q3
Q4
Q5
14
15
13
LE
MR
D
Q6
Q7
4
5
6
7
9
10
11
12
001aah120
Fig 3. Functional diagram
5. Pinning information
5.1 Pinning
74LV259
terminal 1
index area
16 V
CC
15 MR
14 LE
13 D
12 Q7
V
CC(1)
8
9
Q4
11 Q6
10 Q5
GND
A0
2
3
4
5
6
7
1
A1
16 V
CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
9
001aah127
74LV259
A0
A1
A2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
A2
Q0
Q1
Q2
Q3
Q4
001aah117
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16
Fig 5. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
GND
Q[0:7]
74LV259_3
Pin description
Pin
1
2
3
8
4, 5, 6, 7, 9, 10, 11, 12
Description
address input
address input
address input
ground (0 V)
latch output
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 January 2008
3 of 19
NXP Semiconductors
74LV259
8-bit addressable latch
Table 2.
Symbol
D
LE
MR
V
CC
Pin description
…continued
Pin
13
14
15
16
Description
data input
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
6. Functional description
Table 3.
Mode select table
H = HIGH voltage level; L = LOW voltage level
LE
L
H
L
H
MR
H
H
L
L
Mode
addressable latch
memory
active HIGH 8-channel demultiplexer
reset
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = High or LOW data one set-up time prior to the
LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared
Operating modes
master reset
demultiplex (active
HIGH) decoder
(when D = H)
Input
MR
L
L
L
L
L
L
L
L
L
store (do nothing)
addressable latch
H
H
H
H
H
H
H
H
H
LE
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
H
A0
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
A1
X
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
A2
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
Output
Q0
L
Q=d
L
L
L
L
L
L
L
q0
Q=d
q0
q0
q0
q0
q0
q0
q0
Q1
L
L
Q=d
L
L
L
L
L
L
q1
q1
Q=d
q1
q1
q1
q1
q1
q1
Q2
L
L
L
Q=d
L
L
L
L
L
q2
q2
q2
Q=d
q2
q2
q2
q2
q2
Q3
L
L
L
L
Q=d
L
L
L
L
q3
q3
q3
q3
Q=d
q3
q3
q3
q3
Q4
L
L
L
L
L
Q=d
L
L
L
q4
q4
q4
q4
q4
Q=d
q4
q4
q4
Q5
L
L
L
L
L
L
Q=d
L
L
q5
q5
q5
q5
q5
q5
q5
q5
Q=d
L
q6
q6
q6
q6
q6
q6
Q=d
q6
Q6
L
L
L
L
L
L
Q7
L
L
L
L
L
L
L
L
Q=d
q7
q7
q7
q7
q7
q7
q7
q7
Q=d
Q = d q6
74LV259_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 January 2008
4 of 19
NXP Semiconductors
74LV259
8-bit addressable latch
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
DIP16 package
SO16 package
(T)SSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
[5]
[2]
[3]
[4]
[5]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−50
−65
-
-
-
-
Max
+4.6
±20
±50
±25
50
-
+150
750
500
500
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 12 mW/K above 70
°C.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
8. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
[1]
Conditions
[1]
Min
1.0
0
0
−40
-
-
-
Typ
3.3
-
-
+25
-
-
-
Max
3.6
V
CC
V
CC
+125
500
200
100
Unit
V
V
V
°C
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
74LV259_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 January 2008
5 of 19
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