74LV125
Quad buffer/line driver; 3-state
Rev. 03 — 7 April 2009
Product data sheet
1. General description
The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC125 and 74HCT125.
The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The
3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE
causes the outputs to assume a high-impedance OFF-state.
2. Features
I
I
I
I
I
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV125N
74LV125D
74LV125DB
74LV125PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
Type number
NXP Semiconductors
74LV125
Quad buffer/line driver; 3-state
4. Functional diagram
2
1
5
4
9
10
12
13
1A
1OE
2A
2OE
1Y
3
2
1
3
2Y
6
1
5
EN1
6
4
3A
3OE
4A
4OE
mna228
3Y
8
9
8
10
4Y
11
12
11
13
nA
nY
nOE
mna229
mna227
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one buffer)
5. Pinning information
5.1 Pinning
74LV125
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
001aaj961
14 V
CC
13 4OE
12 4A
11 4Y
10 3OE
9
8
3A
3Y
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
001aaj921
74LV125
14 V
CC
13 4OE
12 4A
11 4Y
10 3OE
9
8
3A
3Y
Fig 4.
Pin configuration DIP14, SO14
Fig 5.
Pin configuration SSOP14, TSSOP14
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
2 of 15
NXP Semiconductors
74LV125
Quad buffer/line driver; 3-state
5.2 Pin description
Table 2.
Symbol
1OE, 2OE, 3OE, 4OE,
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin description
Pin
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
Description
output enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Control
nOE
L
L
H
[1]
Function table
[1]
Input
nA
L
H
X
Output
nY
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
DIP14
SO14, SSOP14, TSSOP14
[1]
[2]
[2]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−70
−65
-
-
Max
+7.0
±20
±50
±35
70
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 packages: above 70
°C
the value of P
tot
derates linearly with 12 mW/K.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
3 of 15
NXP Semiconductors
74LV125
Quad buffer/line driver; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
[1]
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.2 V
I
O
=
−100 µA;
V
CC
= 2.0 V
I
O
=
−100 µA;
V
CC
= 2.7 V
I
O
=
−100 µA;
V
CC
= 3.0 V
I
O
=
−100 µA;
V
CC
= 4.5 V
I
O
=
−8
mA; V
CC
= 3.0 V
I
O
=
−16
mA; V
CC
= 4.5 V
-
1.8
2.5
2.8
4.3
2.4
3.6
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
V
V
V
V
V
V
V
−40 °C
to +85
°C
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
−40 °C
to +125
°C
Unit
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
V
V
V
V
V
V
V
0.3V
CC
V
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
4 of 15
NXP Semiconductors
74LV125
Quad buffer/line driver; 3-state
Table 6.
Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
OL
LOW-level output voltage
Conditions
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.2 V
I
O
= 100
µA;
V
CC
= 2.0 V
I
O
= 100
µA;
V
CC
= 2.7 V
I
O
= 100
µA;
V
CC
= 3.0 V
I
O
= 100
µA;
V
CC
= 4.5 V
I
O
= 8 mA; V
CC
= 3.0 V
I
O
= 16 mA; V
CC
= 4.5 V
I
I
I
OZ
input leakage current
OFF-state output current
V
I
= V
CC
or GND;
V
CC
= 5.5 V
V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND;
V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input; V
I
= V
CC
−
0.6 V;
V
CC
= 2.7 V to 3.6 V
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0.20
0.35
-
-
-
0.2
0.2
0.2
0.2
0.40
0.55
1.0
5
-
-
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.50
0.65
1.0
10
V
V
V
V
V
V
V
µA
µA
−40 °C
to +85
°C
Min
Typ
[1]
Max
−40 °C
to +125
°C
Unit
Min
Max
I
CC
∆I
CC
C
I
[1]
supply current
additional supply current
input capacitance
-
-
-
-
-
3.5
20
500
-
-
-
-
160
850
-
µA
µA
pF
Typical values are measured at T
amb
= 25
°C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Figure 8.
Symbol Parameter
t
pd
propagation delay
Conditions
nA to nY; see
Figure 6
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V; C
L
= 15 pF
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
t
en
enable time
nOE to nY; see
Figure 7
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
[3]
[2]
[3]
[3]
[2]
−40 °C
to +85
°C
Min
-
-
-
-
-
-
-
-
-
-
-
Typ
[1]
55
19
14
9
10
-
75
26
19
14
-
Max
-
24
18
-
14
12
-
31
23
18
15
−40 °C
to +125
°C
Min
-
-
-
-
-
-
-
-
-
-
-
Max
-
31
23
-
18
15
-
39
29
23
19
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
74LV125_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2009
5 of 15
嵌入式系统
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