Philips Semiconductors
Product specification
PLL with band gap controlled VCO
74HCT9046A
FEATURES
•
Operation power supply voltage range from 4.5 to 5.5 V
•
Low power consumption
•
Inhibit control for ON/OFF keying and for low standby
power consumption
•
Centre frequency up to 17 MHz (typical) at V
CC
= 5.5 V
•
Choice of two phase comparators:
– PC1: EXCLUSIVE-OR
– PC2: Edge-triggered JK flip-flop.
•
No dead zone of PC2
•
Charge pump output on PC2, whose current is set by an
external resistor R
b
•
Centre frequency tolerance
±10%
•
Excellent Voltage Controlled Oscillator (VCO) linearity
•
Low frequency drift with supply voltage and temperature
variations
•
On-chip band gap reference
•
Glitch free operation of VCO, even at very low
frequencies
•
Zero voltage offset due to op-amp buffering
•
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
6 ns.
SYMBOL
f
c
C
I
C
PD
Notes
PARAMETER
VCO centre frequency
input capacitance
power dissipation capacitance per package
APPLICATIONS
•
FM modulation and demodulation where a small centre
frequency tolerance is essential
•
Frequency synthesis and multiplication where a low jitter
is required (e.g. video picture-in-picture)
•
Frequency discrimination
•
Tone decoding
•
Data synchronization and conditioning
•
Voltage-to-frequency conversion
•
Motor-speed control.
GENERAL DESCRIPTION
The 74HCT9046A is a high-speed Si-gate CMOS device.
It is specified in compliance with JEDEC standard no 7A.
CONDITIONS
TYPICAL
3.5
UNIT
MHz
pF
pF
C1 = 40 pF; R1 = 3 kΩ; V
CC
= 5 V 16
notes 1 and 2
20
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. Applies to the phase comparator section only (pin INH = HIGH). For power dissipation of the VCO and demodulator
sections, see Figs 26 to 28.
2003 Oct 30
2
Philips Semiconductors
Product specification
PLL with band gap controlled VCO
74HCT9046A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
74HCT9046AN
74HCT9046AD
74HCT9046APW
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
SYMBOL
GND
PC1_OUT/
PCP_OUT
COMP_IN
VCO_OUT
INH
C1A
C1B
GND
VCO_IN
DEM_OUT
R1
R2
PC2_OUT
DESCRIPTION
ground (0 V) of phase
comparators
phase comparator 1 output or
phase comparator pulse output
comparator input
VCO output
inhibit input
capacitor C1 connection A
capacitor C1 connection B
ground (0 V) VCO
VCO input
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output;
current source adjustable with
R
b
signal input
bias resistor (R
b
) connection
supply voltage
Fig.1 Pin configuration.
C1A
C1B
GND
GND
PC1_OUT/
PCP_OUT
COMP_IN
VCO_OUT
INH
1
2
3
4
PACKAGE
DIP16
SO16
TSSOP16
MATERIAL
plastic
plastic
plastic
CODE
SOT38-1
SOT109-1
SOT403-1
16
16
16
16 VCC
15 RB
14 SIG_IN
13 PC2_OUT
9046A
5
6
7
8
MBD037
12 R2
11 R1
10 DEM_OUT
9
VCO_IN
14
15
16
SIG_IN
RB
V
CC
2003 Oct 30
3
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2003 Oct 30
C1
6
C1A
7
fout
4
COMP_IN
3
fin
14
SIG_IN
PC1
Vref2
12
R2
PCP
R2
VCO
R3
C1B VCO_OUT
PC1_OUT/
PCP_OUT 2
Vref1
11
R1
logic
1
D
CP
Q
RD
Q
up
Philips Semiconductors
PLL with band gap controlled VCO
Fig.5 Logic diagram.
handbook, full pagewidth
5
R1
logic
1
10
R
s
DEM_OUT
Vref1
Vref2
D
CP
Q
down
CHARGE
PUMP
PC2_OUT 13
(1)
R3'
R4
C2
Q
RD
RB 15
Rb
Vref2
BAND
GAP
VCO_IN
9
INH
74HCT9046A
5
(1)
MBD102
Product specification
R3' = R
b
/17
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