74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 6 — 26 January 2015
Product data sheet
1. General description
The 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
no. 7A.
The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all latches.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are
transparent, i.e. a latch output changes state each time its corresponding D input
changes.
When LE is LOW the latches store the information that was present at the D-inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
The 74HC573; 74HCT573 is functionally identical to:
•
74HC563; 74HCT563, but inverted outputs
•
74HC373; 74HCT373, but different pin arrangement
2. Features and benefits
Input levels:
For 74HC573: CMOS level
For 74HCT573: TTL level
Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Temperature range
74HC573N
74HCT534N
74HC573D
74HCT573D
74HC573DB
74HCT573DB
74HC573PW
74HCT573PW
74HC573BQ
74HCT573BQ
40 C
to +125
C
DHVQFN20
40 C
to +125
C
TSSOP20
40 C
to +125
C
SSOP20
40 C
to +125
C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
SOT163-1
SOT339-1
SOT360-1
SOT764-1
40 C
to +125
C
Name
DIP20
Description
plastic dual in-line package; 20 leads (300 mil)
Version
SOT146-1
Type number Package
4. Functional diagram
Fig 1.
Functional diagram
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
2 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Fig 2.
Logic diagram
Fig 3.
Logic symbol
Fig 4.
IEC logic symbol
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
3 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration DIP20, SO20, SSOP20 and
TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
LE
Q[0:7]
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
latch enable input (active HIGH)
supply voltage
19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
4 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
Table 3.
Function table
[1]
Control
OE
Enable and read register (transparent
mode)
Latch and read register
Latch register and disable outputs
L
L
H
LE
H
L
L
Input
Dn
L
H
l
h
l
h
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
Operating mode
Internal
latches
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP20 package
SO20, SSOP20, TSSOP20 and
DHVQFN20 packages
[1]
[2]
For DIP20 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO20: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP20 and TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN20 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
[1]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
-
-
Max
+7
20
20
35
+70
70
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
5 of 21
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
