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74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop
January 2008
74AC74, 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
Features
■
I
CC
reduced by 50%
■
Output source/sink 24mA
■
ACT74 has TTL-compatible inputs
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q)
outputs. Information at the input is transferred to the out-
puts on the positive edge of the clock pulse. Clock trig-
gering occurs at a voltage level of the clock pulse and is
not directly related to the transition time of the positive-
going pulse. After the Clock Pulse input threshold volt-
age has been passed, the Data input is locked out and
information present will not be transferred to the outputs
until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
■
LOW input to S
D
(Set) sets Q to HIGH level
■
LOW input to C
D
(Clear) sets Q to LOW level
■
Clear and Set are independent of clock
■
Simultaneous LOW on C
D
and S
D
makes both Q and
Q HIGH
Ordering Information
Order Number
74AC74SC
74AC74SJ
74AC74MTC
74AC74PC
74ACT74SC
74ACT74SJ
74ACT74MTC
74ACT74PC
Package
Number
M14A
M14D
MTC14
N14A
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
Truth Table
(Each Half)
Inputs
S
D
L
H
L
H
H
H
Outputs
CP
X
X
X
C
D
H
L
L
H
H
H
D
X
X
X
H
L
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
L
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Q
0
(Q
0
)
=
Previous Q (Q) before LOW-to-HIGH Transition of Clock
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
2
74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
3
74AC74, 74ACT74 — Dual D-Type Positive Edge-Triggered Flip-Flop
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com
4
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