INTEGRATED CIRCUITS
74F168*,
74F169
4-bit up/down binary synchronous counter
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification
IC15 Data Handbook
1996 Jan 05
Philips
Semiconductors
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
FEATURES
•
Synchronous counting and loading
•
Up/Down counting
•
Modulo 16 binary counter
•
Two Count Enable inputs for n-bit cascading
•
Positive edge-triggered clock
•
Built-in carry look-ahead capability
•
Presettable for programmable operation
DESCRIPTION
The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down
counter featuring an internal carry look-ahead for applications in
high-speed counting designs. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when instructed by the Count
Enable inputs and internal gating. This mode of operation eliminates
the output spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the flip-flops
on the Low-to-High transition of the clock.
The counter is fully programmable; that is, the outputs may be
preset to either level.
Presetting is synchronous with the clock and takes place regardless
of the levels of the Count Enable inputs. A Low level on the Parallel
Enable (PE) input disables the counter and causes the data at the
D
n
input to be loaded into the counter on the next Low-to-High
transition of the clock.
The direction of counting is controlled by the Up/Down (U/D) input; a
High will cause the count to increase, a Low will cause the count to
decrease.
The carry look-ahead circuitry provides for n-bit synchronous
applications without additional gating. Instrumental in accomplishing
this function are two Count Enable inputs (CET
,
CEP) and a
Terminal Count (TC) output. Both Count Enable inputs must be Low
to count. The CET input is fed forward to enable the TC output. The
TC output thus enabled will produce a Low output pulse with a
duration approximately equal to the High level portion of the Q
0
output. The Low level TC pulse is used to enable successive
cascaded stages.
PIN CONFIGURATION
U/D
CP
D
0
D
1
D
2
D
3
CEP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
TC
Q
0
Q
1
Q
2
Q
3
CET
PE
SF00766
TYPE
74F169
TYPICAL f
MAX
115MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
35mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F169N
N74F169D
PKG
DWG #
SOT38-4
SOT109-1
16-pin plastic DIP
16-pin plastic SO
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D
0
- D
3
CEP
CET
CP
PE
U/D
Q
0
- Q
3
Parallel data inputs
Count Enable parallel input (active Low)
Count Enable Trickle input (active Low)
Clock input (active rising edge)
Parallel Enable input (active Low)
Up/Down count control input
Flip-flop outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
TC
Terminal count output (active Low)
50/33
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
1996 Jan 05
2
853–0350 16190
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
LOGIC SYMBOL
3
4
5
6
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 16
9
M1 [LOAD]
M2 [COUNT]
9
1
2
7
10
PE
U/D
D
0
D
1
D
2
D
3
1
M3 [UP]
M4 [DOWN]
15
10
CP
CEP
CET
Q
0
Q
1
Q
2
Q
3
3
14
13
12
11
4
5
V
CC
= Pin 16
GND = Pin 8
6
TC
15
7
2
G5
G6
2, 3, 5, 6+/C7
2, 4, 5, 6–
3, 5 CT=15
4, 5 CT=0
1, 7D
[1]
[2]
[4]
[8]
14
13
12
11
SF00786
SF00787
FUNCTIONAL DESCRIPTION
The 74F169 uses edge-triggered J-K-type flip-flops and have no
constraints on changing the control or data input signals in either
state of the clock. The only requirement is that the various inputs
attain the desired state at least a setup time before the rising edge
of the clock and remain valid for the recommended hold time
thereafter. The parallel load operation takes precedence over the
other operations, as indicated in the Mode Select Table. When PE is
Low, the data on the D
0
- D
3
inputs enter the flip-flops on the next
rising edge of the Clock. In order for counting to occur, both CEP
and CET must be Low and PE must be High; the U/D input
determines the direction of counting. The Terminal Count (TC)
output is normally High and goes Low, provided that CET is Low,
when a counter reaches zero in the Count Down mode or reaches
15 in the Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. Since the TC signal is
derived by decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a clock
signal is not recommended (see logic equations below).
1) Count Enable = CEP
⋅
CET
⋅
PE
2) Up: TC = Q
0
⋅
Q
3
⋅
(U/D)
⋅
CET
3) Down: TC = Q
0
⋅
Q
1
⋅
Q
2
⋅
Q
3
⋅
(U/D)
⋅
CET
MODE SELECT — FUNCTION TABLE
INPUTS
CP
↑
↑
↑
↑
↑
↑
H =
h =
L =
l =
q =
X =
↑
=
(1) =
U/D
X
X
h
l
X
X
CEP
X
X
l
l
h
X
CET
X
X
l
l
X
X
PE
l
X
h
h
h
h
D
n
l
X
X
X
X
X
OUTPUTS
Q
n
L
H
Count Up
Count Down
q
n
q
n
TC
(1)
(1)
(1)
(1)
(1)
H
OPERATING MODE
Parallel load (Dn→Qn)
Count Up (increment)
Count Down (decrement)
Hold (do nothing)
High voltage level steady state
High voltage level one setup time prior to the Low-to-High clock transition
Low voltage level steady state
Low voltage level one setup time prior to the Low-to-High clock transition
Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
Don’t care
Low-to-High clock transition
The TC is Low when CET is Low and the counter is at Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).
1996 Jan 05
3
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
MODE SELECT TABLE
INPUTS
PE
CEP
CET
U/D
X
H
L
X
X
OPERATING MODE
Load (D
n
→Q
n
)
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)
STATE DIAGRAM
0
1
2
3
4
L
X
X
H
L
L
H
L
L
H
H
X
H
X
H
H = High Voltage
L = Low Voltage Level
X = Don’t care
15
5
14
6
13
7
12
11
10
9
8
COUNT DOWN
COUNT UP
SF00788
LOGIC DIAGRAM
3
D
0
D
Q
14
Q
0
CP Q
D
1
4
D
Q
13
Q
1
CP Q
D
2
5
D
Q
12
Q
2
CP Q
D
3
PE
6
D
Q
11
Q
3
9
CP Q
7
CEP
10
CET
2
1
15
TC
CP
U/D
V
CC
= Pin 16
GND = Pin 8
SF00789
1996 Jan 05
4
Philips Semiconductors
Product specification
4-bit up/down binary synchronous counter
74F169
APPLICATION
CP
U/D
PE
D
0
PE
U/D
CP
CEP
CET
Q
0
Q
1
Q
2
Q
3
TC
D
1
D
2
D
3
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
PE
U/D
CP
CEP
CET
PE
U/D
CP
TC
CEP
CET
PE
U/D
CP
TC
CEP
CET
TC
Q
0
Q
1
Q
2
Q
3
Q
0
Q
1
Q
2
Q
3
Q
0
Q
1
Q
2
Q
3
LEAST SIGNIFICANT
4-BIT COUNTER
MOST SIGNIFICANT
4-BIT COUNTER
SF00790
Figure 1. Synchronous Multistage Counting Scheme
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
STG
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
Min
4.5
2.0
0.8
–18
–1
20
70
LIMITS
Nom
5.0
Max
5.5
V
V
V
mA
mA
mA
°C
UNIT
1996 Jan 05
5
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