Si5351A/B/C-B
I
2
C - P
R O GRA MM A B LE
A
NY
- F
R E Q U E N C Y
CMOS C
L O C K
G
ENERATOR
+ VCXO
Features
www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
I
2
C user definable configuration
Exact frequency synthesis at each output
(0 ppm error)
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: < 70 ps pp, typ
Configurable spread spectrum selectable
at each output
Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
Supports static phase offset
Programmable rise/fall time control
Glitchless frequency changes
Separate voltage supply pins:
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output delay
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compatible
Supports HCSL compatible swing
10-MSOP
20-QFN
Applications
Ordering Information:
See page 28
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5351 is an I
2
C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while
providing reliable operation over a wide tuning range. The Si5351C offers the same
flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
XA
OSC
PLLA
Multi
Synth
0
Multi
Synth
1
PLLB
XA
OSC
PLL
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
XA
OSC
PLLA
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
XB
VC
VCXO
XB
PLLB
XB
CLKIN
I
2
C
SSEN
OEB
N = 2 or 7
Multi
Synth
N
Si5351A
I
2
C
SSEN
OEB
Multi
Synth
7
I
2
C
INTR
OEB
Multi
Synth
7
Si5351B
Si5351C
Rev. 0.75 10/12
Copyright © 2012 by Silicon Laboratories
Si5351A/B/C-B
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5351A/B/C-B
2
Rev. 0.75
Si5351A/B/C-B
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .19
5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
9. Si5351 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1. Si5351A 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9.2. Si5351B 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9.3. Si5351C 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.4. Si5351A 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11.2. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 0.75
3
Si5351A/B/C-B
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
3.0
2.25
1.71
Output Buffer Voltage
V
DDOx
2.25
3.0
Typ
25
3.3
2.5
1.8
2.5
3.3
Max
85
3.60
2.75
1.89
2.75
3.60
Unit
°C
V
V
V
V
V
Notes:All
minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
VDD and VDDOx can be operated at independent voltages.
Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same
time as VDD.
Table 2. DC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Output Buffer Supply Current
(Per Output)*
Input Current
Symbol
I
DD
I
DDOx
I
CLKIN
I
VC
Test Condition
Enabled 3 outputs
Enabled 8 outputs
C
L
= 5 pF
CLKIN, SDA, SCL
Vin < 3.6 V
VC
3.3 V VDDO, default high
drive
Min
—
—
—
—
—
—
Typ
22
27
2.2
—
—
50
Max
35
45
5
10
30
—
Unit
mA
mA
mA
µA
µA
Output Impedance
Z
O
*Note:
Output clocks less than or equal to 100 MHz.
4
Rev. 0.75
Si5351A/B/C-B
Table 3. AC Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Power-up Time
Symbol
T
RDY
Test Condition
From V
DD
= V
DDmin
to valid
output clock, C
L
= 5 pF,
f
CLKn
> 1 MHz
From OEB pulled low to valid
clock output, C
L
= 5 pF,
f
CLKn
> 1 MHz
Down spread
Center spread
Min
—
Typ
1
Max
10
Unit
ms
Output Enable Time
Output Phase Offset
Spread Spectrum Frequency
Deviation
Spread Spectrum Modulation
Rate
VCXO Control Voltage Range
VCXO Gain (configurable)
VCXO Control Voltage Linearity
VCXO Pull Range
(configurable)
VCXO Modulation Bandwidth
T
OE
P
STEP
SS
DEV
SS
MOD
—
—
–0.1
±0.1
30
—
333
—
—
31.5
10
—
–2.5
±1.5
33
µs
ps/step
%
%
kHz
VCXO Specifications (Si5351B only)
Vc
Kv
KVL
PR
Vc = 10–90% of V
DD
, V
DD
= 3.3 V
Vc = 10–90% of V
DD
V
DD
= 3.3 V*
0
18
–5
±30
—
V
DD
/2
—
—
0
10
V
DD
150
+5
±240
—
V
ppm/V
%
ppm
kHz
*Note:
Contact Silicon Labs for 2.5 V VCXO operation.
Table 4. Input Clock Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
CLKIN Input Low Voltage
CLKIN Input High Voltage
CLKIN Frequency Range
Symbol
V
IL
V
IH
f
CLKIN
Test Condition
Min
–0.1
0.7 x V
DD
10
Typ
—
—
—
Max
0.3 x V
DD
3.60
100
Unit
V
V
MHz
Rev. 0.75
5
FPGA/CPLD
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