PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
F
EATURES
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.56ps (typical)
• 3.3V output supply mode
• -40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS844003I-01 is a 3 differential output LVDS
Synthesizer designed to generate Ethernet refer-
HiPerClockS™
ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequen-
cies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 844003I-01 has 2
output banks, Bank A with 1 differential LVDS output pair and
Bank B with 2 differential LVDS output pairs.
ICS
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies men-
tioned above. The ICS844003I-01 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844003I-01 is packaged in a small
24-pin TSSOP package.
P
IN
A
SSIGNMENT
DIV_SELB0
VCO_SEL
MR
V
DDO
_
A
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
V
DDA
V
DD
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
DDO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
B
LOCK
D
IAGRAM
CLK_ENA
Pullup
DIV_SELA[1:0]
Pullup
VCO_SEL
Pullup
ICS844003I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
QA0
0
00
01
10
11
÷1
÷2
÷3
÷4
(default)
TEST_CLK
Pulldown
nQA0
0
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
1
QB0
FB_DIV
0 = ÷25 (default)
1 = ÷32
00
01
10
11
÷2
÷4
÷5
÷8
(default)
nQB0
QB1
nQB1
FB_DIV
Pulldown
DIV_SELB[1:0]
Pullup
MR
Pulldown
CLK_ENB
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI-01
www.icst.com/products/hiperclocks.html
1
REV. A MAY 31, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
Type
Description
Division select pin for Bank B. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels. See Table 3C.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
Pullup
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state
of outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Synchronizing clock enable for Bank B outputs. Active High output enable.
When logic HIGH, the output pair in Bank B is enabled. When logic LOW,
the QB outputs are LOW and nQB outputs are HIGH. Has an internal
pullup resistor so the default power-up state of output is enabled.
LVCMOS/LVTTL interface levels. See Figure 1.
Synchronizing clock enable for Bank A outputs. Active High output enable.
When logic HIGH, the output pair in Bank A is enabled. When logic LOW,
the QA output is LOW and nQA output is HIGH. Has an internal pullup
resistor so the default power-up state of output is enabled.
LVCMOS/LVTTL interface levels. See Figure 1.
Feedback divide select. When Low (default), the feedback divider is set
for ÷25. When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels. See Table 3D.
Analog supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1,
24
2
Name
DIV_SELB0,
DIV_SELB1
VCO_SEL
Input
Input
3
MR
Input
4
5, 6
V
DDO_A
QA0, nQA0
Power
Ouput
7
CLK_ENB
Input
Pullup
8
CLK_ENA
Input
Pullup
9
10
11
12,
13
14
15, 16
FB_DIV
V
DDA
V
DD
DIV_SELA0,
DIV_SELA1
GND
XTAL_OUT,
XTAL_IN
TEST_CLK
Input
Power
Power
Input
Power
Input
Pulldown
17
Input
18
19, 20
21, 22
XTAL_SEL
nQB1, QB1
nQB0, QB0
Input
Output
Output
Core supply pin.
Division select pin for Bank A. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels. See Table 3C.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is
the input. XTAL_IN is also the overdrive pin if you want to overdrive the
crystal circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
Pulldown pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected
Pullup
by default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power
Output supply pin for Bank B outputs.
23
V
DDO_B
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
844003AGI-01
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
www.icst.com/products/hiperclocks.html
2
REV. A MAY 31, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_A
= V
DDO_B
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO_A, B
I
DD
I
DDA
I
DDO_A, B
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
102
10
50
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_A
= V
DDO_B
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
TEST_CLK, MR, FB_DIV
DIV_SELB0, DIV_SELB1,
DIV_SELA0, DIV_SELA1,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
TEST_CLK, MR, FB_DIV
DIV_SELB0, DIV_SELB1,
DIV_SELA0, DIV_SELA1,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
Test Conditions
V
DD
= 3.3V
V
DD
= 3.3V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IH
I
IL
Input
Low Current
844003AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A MAY 31, 2005
工业自动化与控制
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