FemtoClock
®
Crystal-to-3.3V LVDS
Frequency Synthesizer
Datasheet
844003
General Description
The 844003 is a three differential output LVDS Synthesizer designed
to generate Ethernet reference clock frequencies. Using a 31.25MHz
or 26.041666MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the settings of four
frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 844003 has two output
banks, Bank A with one differential LVDS output pair and
Bank B with two differential LVDS output pairs.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
844003 uses IDT’s 3
rd
generation low phase noise VCO technology
and can achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The 844003 is packaged in a small
24-pin TSSOP package.
Features
•
•
•
•
•
•
•
•
Three LVDS outputs on two banks, A Bank with one LVDS pair
and B Bank with two LVDS output pairs
Using a 31.25MHz or 26.041666MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 560MHz to 700MHz
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.63ps (typical)
3.3V output supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Pin Assignment
DIV_SELB0
VCO_SEL
MR
V
DDO_A
QA0
nQA0
OEB
OEA
FB_DIV
V
DDA
V
DD
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
DDO_B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
Block Diagram
844003
24-Lead TSSOP
OEA
DIV_SELA[1:0]
VCO_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Pullup
Pulldown:Pullup
Pullup
00
01
10
11
÷1
÷2
(default)
÷4
÷5
4.40mm x 7.8mm x 0.92mm
package body
QA0
nQA0
G Package
Top View
Pulldown
0
0
Phase
Detector
FB_DIV
VCO
1
QB0
00
01
10
11
÷1
÷2
÷4
(default)
÷5
0 = ÷20 (default)
1 = ÷24
FB_DIV
DIV_SELB[1:0]
MR
OEB
Pulldown
Pullup:Pulldown
Pulldown
Pullup
nQB0
QB1
nQB1
©2016 Integrated Device Technology, Inc.
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January 29, 2016
844003 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
Name
DIV_SELB0
Input
Type
Pulldown
Description
Division select pin for Bank B. LVCMOS/LVTTL interface levels. See Table 3C.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
TEST_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an
internal pulldown resistor so the power-up default state of outputs and dividers
are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH, the
output pairs on Bank B are enabled. When logic LOW, the output pairs are in a
high impedance state. Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3F.
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair in Bank A is enabled. When logic LOW, the output pair is in a high
impedance state. Has an internal pullup resistor so the default power-up state of
output is enabled. LVCMOS/LVTTL interface levels. See Table 3E.
Feedback divide select. When Low (default), the feedback divider is set for ÷20.
When HIGH, the feedback divider is set for ÷24. See Table 3D
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pullup
Pulldown
Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C.
Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output.
Parallel resonant crystal interface. XTAL_IN is the input. XTAL_IN is also the
overdrive pin if you want to overdrive the crystal circuit with a single-ended
reference clock.
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to
low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
2
VCO_SEL
Input
Pullup
3
MR
Input
Pulldown
4
5
6
V
DDO_A
QA0
nQA0
Power
Output
Output
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12
13
14
15
16
FB_DIV
V
DDA
V
DD
DIV_SELA0
DIV_SELA1
GND
XTAL_OUT
XTAL_IN
Input
Power
Power
Input
Input
Power
Output
Input
Pulldown
17
TEST_CLK
Input
18
19
20
XTAL_SEL
nQB1
QB1
Input
Output
Output
Pullup
©2016 Integrated Device Technology, Inc.
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January 29, 2016
844003 Datasheet
Number
21
22
23
24
Name
nQB0
QB0
V
DDO_B
DIV_SELB1
Output
Output
Power
Input
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pin for Bank B outputs.
Pullup
Division select pin for Bank B. LVCMOS/LVTTL interface levels. See Table 3C.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input
Capacitance
LVCMOS/
LVTTL Inputs
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Input Pulldown Resistor
Input Pullup Resistor
©2016 Integrated Device Technology, Inc.
3
January 29, 2016
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