requirements. The ICS844003 is packaged in a small 24-
pin TSSOP package.
P
IN
A
SSIGNMENT
DIV_SELB0
VCO_SEL
MR
V
DDO
_
A
QA0
nQA0
OEB
OEA
FB_DIV
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
DDO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
B
LOCK
D
IAGRAM
OEA
Pullup
DIV_SELA[1:0]
VCO_SEL
Pullup
V
DDA
V
DD
DIV_SELA0
ICS844003
QA0
TEST_CLK
Pulldown
0
0
00
01
10
11
÷1
÷2
(default)
÷4
÷5
nQA0
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
1
QB0
FB_DIV
0 = ÷20 (default)
1 = ÷24
00
01
10
11
÷1
÷2
÷4
(default)
÷5
nQB0
QB1
nQB1
FB_DIV
Pulldown
DIV_SELB[1:0]
MR
Pulldown
OEB
Pullup
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
1
ICS844003AG REV A FEBRUARY 25, 2009
ICS844003
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
24
2
Name
DIV_SELB0
DIV_SELB1
VCO_SEL
Type
Input
Description
Division select pin for Bank B. Default = Low.
Pulldown
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the cr ystal reference
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
Pullup
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH,
the output pairs on Bank B are enabled. When logic LOW, the output pairs
are in a high impedance state. Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH,
the output pair in Bank A is enabled. When logic LOW, the output pair is in
a high impedance state. Has an internal pullup resistor so the default
power-up state of output is enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
for ÷20. When HIGH, the feedback divider is set for ÷24.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Input
3
MR
Input
4
5, 6
7
V
DDO_A
QA0, nQA0
OEB
Power
Ouput
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12
13
14
15, 16
FB_DIV
V
DDA
V
DD
DIV_SELA0
DIV_SELA1
GND
XTAL_OUT,
XTAL_IN
TEST_CLK
Input
Power
Power
Input
Power
Input
Pulldown
17
Input
18
19, 20
21, 22
XTAL_SEL
nQB1, QB1
nQB0, QB0
Input
Output
Output
Core supply pin.
Division select pin for Bank A. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels.
Power supply ground.
Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the cr ystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
Pulldown pull to low state by default. Can leave floating if using the cr ystal interface.
LVCMOS/LVTTL interface levels.
Cr ystal select pin. Selects between the single-ended TEST_CLK or cr ystal
Pullup
interface. Has an internal pullup resistor so the cr ystal interface is selected
by default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power
Output supply pin for Bank B outputs.
23
V
DDO_B
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
2
ICS844003AG REV A FEBRUARY 25, 2009
ICS844003
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
3A. B
ANK
A F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
DIV_SELA1
0
0
1
1
0
0
1
1
DIV_SELA0
0
1
0
1
0
1
0
1
FB_DIV
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank A
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
64.8
QA0/nQA0
Output
Frequency
(MHz)
625
312.5
156.25
12 5
62 5
312.5
156.25
125
T
ABLE
3B. B
ANK
B F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
DIV_SELB1
0
0
1
1
0
0
1
1
DIV_SELB0
0
1
0
1
0
1
0
1
FB_DIV
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank B
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
QB0/nQB0
Output
Frequency
(MHz)
625
312.5
156.25
125
625
312.5
156.25
125
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
3
ICS844003AG REV A FEBRUARY 25, 2009
ICS844003
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
3C. O
UTPUT
B
ANK
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Outputs
QA
÷1
÷2
÷4
÷5
0
0
1
1
Inputs
DIV_SELB1
DIV_SELB0
0
1
0
1
Outputs
QB
÷1
÷2
÷4
÷5
T
ABLE
3D. F
EEDBACK
D
IVIDER
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_DIV
0
1
Feedback Divide
÷20
÷24
T
ABLE
3E. OEA S
ELECT
F
UNCTION
T
ABLE
Inputs
OEA
0
1
QA0
LOW
Active
Outputs
nQA0
HIGH
Active
T
ABLE
3F. OEB S
ELECT
F
UNCTION
T
ABLE
Inputs
OEB
0
1
LOW
Active
Outputs
QB0:QB1
nQB0:nQB1
HIGH
Active
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
4
ICS844003AG REV A FEBRUARY 25, 2009
ICS844003
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
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