VCXO Jitter Attenuator &
FemtoClock
™
Multiplier
ICS813323
DATA SHEET
General Description
The ICS813323 is a PLL based synchronous multiplier
that is optimized for SONET clock jitter attenuation and
HiPerClockS™
frequency translation. The device contains two internal
frequency multiplication stages which are cascaded in
series. The first stage is a VCXO PLL that is optimized
to provide reference clock jitter attenuation. The second stage is a
FemtoClock™ frequency multiplier that provides a low jitter, high
frequency SONET output clock.
Features
•
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•
•
•
•
•
•
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Three differential LVPECL output pairs
One differential input supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 19.44MHz to 622.08MHz,
including: 77.76MHz and 155.52MHz input clocks
Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
Outputs common SONET clock rates
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
Absolute pull range: ±50ppm
FemtoClock frequency multiplier provides low jitter,
high frequency output
FemtoClock frequency: 622.08MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz – 20MHz): 1.4ps (typical)
Full 3.3V supply, or mixed 3.3V core/2.5V output supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
ICS
Pre-divider and output divider multiplication ratios are selected using
device selection control pins. The multiplication ratios are optimized
to support most common clock rates used in SONET applications.
The VCXO requires the use of an external, inexpensive pullable
crystal. The VCXO uses external passive loop filter components
which allows configuration of the PLL loop bandwidth and damping
characteristics.
Pin Assignment
LF
V
CCA
V
CC
V
CCO
nQ0
Q0
PSEL0
V
EE
PSEL1
XTAL_OUT
XTAL_IN
V
EE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
V
CCO
nQ2
Q2
nQ1
Q1
FSEL0
V
EE
FSEL1
nBYPASS
CLK
nCLK
ICS813323
24 Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
XTAL_IN
Block Diagram
External
Loop Filter Input
nBypass
Pullup
XTAL_OUT
19.44MHz
Q0
0
CLK
Pulldown
nCLK
Pullup/Pulldown
PSEL[1:0]
Pullup
2
Pre-Divider
1, 4, 8, 32
Phase
Detector
VCXO
19.44MHz
Phase Detector
Loop Filter
Output
Divider
1, 4, 8, 32
nQ0
Q1
nQ1
VCO
622.08MHz
1
÷32
Q2
nQ2
VCXO Jitter Attenuation PLL
FSEL[1:0]
Pullup
OE
Pullup
FemtoClock Frequency Multiplier
2
ICS813323BG REVISION A APRIL 13, 2010
1
©2010 Integrated Device Technology, Inc.
ICS813323 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
™
MULTIPLIER
Table 1. Pin Descriptions
Number
1
2
3
4, 23
5, 6
19, 20
21, 22
7,
9
8, 12, 17
10,
11
13
14
15
16,
18
24
Name
LF
V
CCA
V
CC
V
CCO
nQ0, Q0
Q1, nQ1
Q2, nQ2
PSEL0,
PSEL1
V
EE
XTAL_OUT,
XTAL_IN
nCLK
CLK
nBypass
FSEL1,
FSEL0
OE
Type
Analog
Input/Output
Power
Power
Power
Output
Description
Loop filter connection node pin.
Analog supply pin.
Core supply pin.
Output power supply pins.
Differential clock outputs. LVPECL interface levels.
Input
Power
Input
Input
Input
Input
Input
Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Negative supply pins.
VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the
output.
Pullup/
Pulldown
Pulldown
Pullup
Pullup
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
PLL Bypass control pin. See Table 3D.
Select pins. See Table 3B.
Output enable. When logic LOW, the clock outputs are in High-Impedance.
When logic HIGH, the clock outputs are enabled. LVCMOS/LVTTL interface
levels. See Table 3C.
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3A. Pre-Divider Selection Function Table
Inputs
PSEL1
0
0
1
1
PSEL0
0
1
0
1
Pre-Divider Value
÷1
÷4
÷8
÷32 (default)
FSEL1
0
0
1
1
Table 3B. FSEL Function Table
Inputs
FSEL0
0
1
0
1
Output Divider Value
÷1
÷4
÷8
÷32 (default)
ICS813323BG REVISION A APRIL 13, 2010
2
©2010 Integrated Device Technology, Inc.
ICS813323 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
™
MULTIPLIER
Table 3C. OE Function Table
Input
OE
0
1
Clock Outputs
Q[0:2]
LOW
Enabled
nQ[0:2]
HIGH
Enabled
Table 3D. Bypass Function Table
nBypass Input
0
1 (default)
Operation
VCXO jitter attenuation PLL and FemtoClock multiplier bypassed. Input passed directly to N divider.
Normal operation mode.
Table 3E. Frequency Function Table
Input Frequency
(MHz)
19.44
19.44
19.44
19.44
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
622.08
622.08
622.08
622.08
Input
Divider
÷1
÷1
÷1
÷1
÷4
÷4
÷4
÷4
÷8
÷8
÷8
÷8
÷32
÷32
÷32
÷32
VCXO Crystal
Frequency
(MHz)
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
FemtoClock
Feedback Divider
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
FemtoClock
VCO Frequency
(MHz)
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
622.08
Output Divider
Value
÷1
÷4
÷8
÷32
÷1
÷4
÷8
÷32
÷1
÷4
÷8
÷32
÷1
÷4
÷8
÷32
Output Frequency
(MHz)
622.08
155.52
77.76
19.44
622.08
155.52
77.76
19.44
622.08
155.52
77.76
19.44
622.08
155.52
77.76
19.44
ICS813323BG REVISION A APRIL 13, 2010
3
©2010 Integrated Device Technology, Inc.
ICS813323 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
™
MULTIPLIER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
82.3°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.15
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
130
15
Units
V
V
V
mA
mA
Table 4B. LVPECL Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.15
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
CC
2.625
130
15
Units
V
V
V
mA
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
OE, PSEL[0:1],
nBypass, FSEL[0:1]
OE, PSEL[0:1],
nBypass, FSEL[0:1]
V
CC
= V
IN
= 3.465V
V
CC
= 3.465, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
Units
V
V
µA
µA
ICS813323BG REVISION A APRIL 13, 2010
4
©2010 Integrated Device Technology, Inc.
ICS813323 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
™
MULTIPLIER
Table 4D. Differential DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1
CLK, nCLK
nCLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
0.15
V
EE
+ 0.5
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1. Common mode voltage is defined as V
IH
.
Table 4E. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.4
V
CCO
– 2.0
0.6
Typical
Maximum
V
CCO
– 0.9
V
CCO
– 1.7
1.0
Units
µA
µA
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
– 2V.
Table 4F. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.4
V
CCO
– 2.0
0.4
Typical
Maximum
V
CCO
– 0.9
V
CCO
– 1.5
1.0
Units
µA
µA
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
– 2V.
ICS813323BG REVISION A APRIL 13, 2010
5
©2010 Integrated Device Technology, Inc.
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