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74VHC175 Quad D-Type Flip-Flop
May 2007
74VHC175
Quad D-Type Flip-Flop
Features
■
High Speed: f
MAX
=
210MHz (Typ.) at V
CC
=
5V
■
Low power dissipation: I
CC
=
4µA (Max.) at T
A
=
25°C
■
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
■
Power down protection is provided on all inputs
■
Low noise: V
OLP
=
0.8V (Max.)
■
Pin and function compatible with 74HC175
tm
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on
the D inputs is stored during the LOW-to-HIGH clock
transition. Both true and complemented outputs of each
flip-flop are provided. A Master Reset input resets all flip-
flops, independent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Order Number
74VHC175M
74VHC175SJ
74VHC175MTC
Package
Number
M16A
M16D
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
Connection Diagram
Pin Description
Pin Names
D
0
–D
3
CP
MR
Q
0
–Q
3
Q
0
–Q
3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
©1993 Fairchild Semiconductor Corporation
74VHC175 Rev. 1.2
www.fairchildsemi.com
74VHC175 Quad D-Type Flip-Flop
Logic Symbol
Functional Description
The VHC175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock
and Master Reset are common. The four flip-flops will
store the state of their individual D inputs on the LOW-to-
HIGH clock (CP) transition, causing individual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q outputs HIGH inde-
pendent of Clock or Data inputs. The VHC175 is useful
for general logic applications where a common Master
Reset and Clock are acceptable.
Truth Table
IEEE/IEC
Inputs @ t
n
,
MR
=
H
D
n
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Outputs @ t
n+1
Q
n
L
H
Q
n
H
L
t
n
=
Bit Time before Clock Pulse
t
n+1
=
Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1993 Fairchild Semiconductor Corporation
74VHC175 Rev. 1.2
www.fairchildsemi.com
2
74VHC175 Quad D-Type Flip-Flop
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
OPR
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
Parameter
Rating
2.0V to +5.5V
0V to +5.5V
0V to V
CC
–40°C to +85°C
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74VHC175 Rev. 1.2
www.fairchildsemi.com
3
74VHC175 Quad D-Type Flip-Flop
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C to
+85°C
Max.
Min.
1.50
0.7 x V
CC
0.50
0.3 x V
CC
0.50
0.3 x V
CC
1.9
2.9
4.4
2.48
3.80
V
V
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0–5.5
2.0
3.0–5.5
2.0
3.0
4.5
3.0
4.5
Conditions
Min.
1.50
0.7 x V
CC
Typ.
Max.
Units
V
V
IN
=
V
IH
or V
IL
I
OH
=
–50µA
1.9
2.9
4.4
2.0
3.0
4.5
I
OH
=
–4mA
I
OH
=
–8mA
V
IN
=
V
IH
or V
IL
I
OL
=
50µA
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
4.0
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
0.1
0.1
0.1
0.44
0.44
±1.0
40.0
V
I
OL
=
4mA
I
OL
=
8mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
I
IN
I
CC
Input Leakage
Current
Quiescent
Supply Current
0–5.5
5.5
µA
µA
Noise Characteristics
T
A
=
25°C
Symbol
V
OLP(2)
V
OLV(2)
V
IHD(2)
V
ILD(2)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level Dynamic
Input Voltage
Maximum LOW Level Dynamic
Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Typ.
0.4
–0.4
Limits
0.8
–0.8
3.5
1.5
Units
V
V
V
V
Conditions
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
Note:
2. Parameter guaranteed by design.
©1993 Fairchild Semiconductor Corporation
74VHC175 Rev. 1.2
www.fairchildsemi.com
4
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