CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ICS843004-02
G
ENERAL
D
ESCRIPTION
The ICS843004-02 is a 4 output LVPECL
Synthesizer optimized to generate clock
HiPerClockS™
frequencies for a variety of high performance
applications and is a member of the HiPerClocks
TM
family of high performance clock solutions from
IDT. This device can select its input reference clock from either
a crystal input or a single-ended clock signal and can be
configured to generate a number of different output frequen-
cies via the 3 frequency select pins (F_SEL2:0). The
ICS843004-02 uses IDT’ 3rd generation low phase noise
VCO technology and can achieve 1ps or lower typical rms
phase jitter. This ensures that it will easily meet clocking
requirements for high-speed communication protocols such as
10 and 12 Gigabit Ethernet, 10 Gigbit Fibre Channel, and
SONET. This device is also suitable for next generation serial I/
O technologies like serial ATA and SCSI and is conveniently
packaged in a small 24-pin TSSOP package.
F
EATURES
• Four 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Output frequency range: 70MHz - 680MHz
• Crystal input range: 14MHz - 37.78MHz
• VCO Range: 560MHz - 680MHz
• Supports the following applications: Fibre Channel,
SONET, Ethernet, Serial ATA, SCSI and HDTV
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.91ps (typical)
Offset
Noise Power
100Hz ............... -97.1 dBc/Hz
1kHz ............. -121.6 dBc/Hz
10kHz ............. -124.9 dBc/Hz
100kHz ............. -125.1 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
ICS
F
UNCTION
T
ABLE
Inputs
F_SEL2
0
0
0
0
1
1
1
1
F_SEL1 F_SEL0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
M Divider
Value
18
24
24
32
32
32
32
40
N Divider
Value
3
4
8
1
2
4
8
8
P
IN
A
SSIGNMENT
B
LOCK
D
IAGRAM
nPLL_SEL
Pulldown
nQ1
Q1
V
CC
o
Q0
nQ0
MR
nPLL_SEL
nc
nc
V
CCA
F_SEL0
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
CCO
Q3
nQ3
F_SEL2
nXTAL_SEL
REF_CLK
V
EE
XTAL_IN
XTAL_OUT
F_SEL1
N
Q0
XTAL_IN
ICS843004-02
nQ0
Q1
nQ1
OSC
XTAL_OUT
REF_CLK
Pulldown
0
÷1
÷2
1
÷3
÷4
(default)
÷8
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
1
Phase
Detector
VCO
0
nXTAL_SEL
Pulldown
Q2
M
÷18
÷24
÷32
(default)
÷40
nQ2
Q3
nQ3
MR
Pulldown
3
F_SEL0:2
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843004AG-02 REV A JULY 30,2007
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
Name
nQ1, Q1
V
CCO
Q0, nQ0
MR
Type
Output
Power
Ouput
Input
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, selects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pullup
Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Negative supply pin.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between cr ystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
7
8, 9
10
11,
19
12
13
14,
15
16
17
18
20, 21
23, 24
nPLL_SEL
nc
V
CCA
F_SEL0,
F_SEL2
V
CC
F_SEL1
XTAL_OUT,
XTAL_IN
V
EE
REF_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Input
Power
Input
Input
Output
Output
NOTE:
Pulldown and Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843004AG-02 REV A JULY 30, 2007
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
3. O
UTPUT
C
ONFIGURATION AND
F
REQUENCY
R
ANGE
F
UNCTION
T
ABLE
Inputs
F_SEL2
0
1
1
1
1
0
1
0
0
0
1
0
F_SEL1 F_SEL0
1
1
1
0
1
1
0
0
1
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
REF_CLK
24.75
14.8351649
16
19.44
19.44
19.44
19.44
25
25
26.5625
19.53125
31.25
M Divider
Value
24
40
40
32
32
32
32
24
24
24
32
18
N Divider
Value
8
8
8
4
8
1
2
4
8
4
4
3
VCO
(MHz)
594
593.4066
640
622.08
622.08
622.08
622.08
600
600
637.5
625
562.5
Output
Frequency
(MHz)
74.25
74.1758245
80
155.52
77.76
622.08
311.04
150
75
159.375
156.25
187.5
Application
HDTV
HDTV
SCSI
SONET
SONET
SONET
SONET
SATA
SATA
10 Gig Fibre Channel
10 Gig Ethernet
12 Gig Ethernet
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843004AG-02 REV A JULY 30, 2007
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
70°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.12
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
150
12
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
nPLL_SEL, nXTAL_SEL,
Input
F_SEL0:F_SEL2, MR
Low Voltage
REF_CLK
Input
High Current
REF_CLK, MR, F_SEL1
nPLL_SEL, nXTAL_SEL
F_SEL0, F_SEL2
I
IL
Input
Low Current
REF_CLK, MR, F_SEL1
nPLL_SEL, nXTAL_SEL,
F_SEL0, F_SEL2
Test Conditions
Minimum Typical
2
-0.3
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
Maximum
V
CC
+ 0.3
0.8
1.3
150
5
Units
V
V
V
µA
µA
µA
µA
I
IH
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843004AG-02 REV A JULY 30, 2007
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
14
Test Conditions
Minimum
Typical
Maximum
37.78
50
7
1
Units
MHz
MHz
Ω
pF
mW
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C
TO
70°C
Symbol
f
OUT
f
VCO
Parameter
Output Frequency
PLL VCO Lock Range
Output Skew; NOTE 1
RMS Phase Jitter ; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
155.52MHz, 12kHz -20MHz
75MHz, 900kHz -7.5MHz
20% to 80%
200
0.91
0.76
500
54
52
F_SEL{2:0]
≠
000
F_SEL{2:0] = 000
Test Conditions
Minimum
70
560
560
Typical
Maximum
680
68 0
580
25
Units
MHz
MHz
MHz
ps
ps
ps
ps
%
%
t
sk(o)
t
jit(Ø)
t
R
/ t
F
odc
Odd N Divider
46
Even N Divider
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: Phase jitter is measured using the cr ystal input.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS843004AG-02 REV A JULY 30, 2007
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