700MHZ, FemtoClock
®
VCXO Based
Sonet/SDH Jitter Attenuators
843002I-41
DATA SHEET
General Description
The ICS843002I-41 is a PLL based synchronous clock generator
that is optimized for SONET/SDH line card applications where
jitter attenuation and frequency translation is needed. The device
contains two internal PLL stages that are cascaded in series. The
first PLL stage uses a VCXO which is optimized to provide
reference clock jitter attenuation and to be jitter tolerant, and to
provide a stable reference clock for the 2nd PLL stage (typically
19.44MHz). The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a low
phase noise FemtoClock™VCO. PLL multiplication ratios are
selected from internal lookup tables using device input selection
pins. The device performance and the PLL multiplication ratios are
optimized to support non-FEC (non-Forward Error Correction)
SONET/SDH applications with rates up to OC-48 (SONET) or
STM-16 (SDH). The VCXO requires the use of an external,
inexpensive pullable crystal. VCXO PLL uses external passive
loop filter components which are used to optimize the PLL loop
bandwidth and damping characteristics for the given
line card application.
The ICS843002I-41 includes two clock input ports. Each one can
accept either a single-ended or differential input. Each input port
also includes an activity detector circuit, which reports input clock
activity through the LOR0 and LOR1 logic output pins. The two
input ports feed an input selection mux. “Hitless switching” is
accomplished through proper filter tuning. Jitter transfer and
wander characteristics are influenced by loop filter tuning, and
phase transient performance is influenced by both loop filter
tuning and alignment error between the two reference clocks.
Typical ICS843002I-41 configuration in SONET/SDH Systems:
Features
•
•
•
•
•
•
•
•
•
Two Differential LVPECL outputs
Selectable CLKx, nCLKx differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
Maximum output frequency: 700MHz
FemtoClock VCO frequency range: 560MHz - 700MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
Full 3.3V or mixed 3.3V core/2.5V output operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
XTAL_OUT
XTAL_IN
R_SEL1
R_SEL2
R_SEL0
nCLK1
CLK1
V
EE
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
CC
CLK0
nCLK0
CLK_SEL
QA_SEL2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
CCA
QA_SEL0
QA_SEL1
QB_SEL2
QB_SEL1
QB_SEL0
nQA
QA
24
23
22
21
20
19
18
17
LOR0
LOR1
nc
V
CCO_LVCMOS
V
CCO_LVPECL
nQB
QB
V
EE
•
•
•
VCXO 19.44MHz crystal
Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz
Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz,
Hi-Z
ICS843002I-41
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
843002I-41 Rev B 9/4/14
1
©2014 Integrated Device Technology, Inc.
843002I-41 DATA SHEET
Table 1. Pin Descriptions
Number
1, 2
3
4
5
6
7
8
9,
10
11
12,
13
14
15, 16
17, 27
18, 19
20
21
22
23
24
25
26
28,
29,
30
31,
32
Name
LF1, LF0
ISET
V
CC
CLK0
nCLK0
CLK_SEL
QA_SEL2
QA_SEL1,
QA_SEL0
QB_SEL2
QB_SEL1,
QB_SEL0
V
CCA
QA, nQA
V
EE
QB, nQB
V
CCO_LVPECL
V
CCO_LVCMOS
nc
LOR1
LOR0
nCLK1
CLK1
R_SEL0,
R_SEL1,
R_SEL2
XTAL_OUT,
XTAL_IN
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Input
Input
Input
Input
Input
Input
Power
Output
Power
Output
Power
Power
Unused
Output
Output
Input
Input
Input
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Description
Loop filter connection node pins.
Charge pump current setting pin.
Core power supply pin.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Input clock select. LVCMOS/LVTTL interface levels. See Table 3A.
Output divider control for QA/nQA LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
Output divider control for QA/nQA LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
Output divider control for QB/nQB LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
Output divider control for QB/nQB LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
Analog supply pin.
Differential clock output pair. LVPECL interface levels.
Negative supply pins.
Differential clock output pair. LVPECL interface levels.
Output supply pin for LVPECL outputs.
Output supply pin for LVCMOS/LVTTL outputs.
No connect.
Alarm output, loss of reference for CLK1/nCLK1.
LVCMOS/LVTTL interface levels.
Alarm output, loss of reference for CLK0/nCLK0.
LVCMOS/LVTTL interface levels.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B.
Crystal oscillator interface. The XTAL_IN is the input.
XTAL_OUT is the output.
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER
ATTENUATOR
3
Rev B 9/4/14
843002I-41 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
(LVCMOS)
Outputs, I
O
(LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CCO_LVCMOS
+ 0.5V
50mA
100mA
37C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V±5%, V
CCO_LVCMOS,
V
CCO_LVPECL
= 3.3V±5% or 2.5V±5%, V
EE
= 0V,
T
A
= -40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO_LVCMOS,
V
CCO_LVPECL
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
2.375
Power Supply Current
Analog Supply Current
2.5
2.625
210
15
V
mA
mA
Test Conditions
Minimum
3.135
V
CC
– 0.15
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
Units
V
V
V
700MHZ, FEMTOCLOCK™ VCXO BASED SONET/SDH JITTER
ATTENUATOR
5
Rev B 9/4/14
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