700MHZ, Low Jitter, Crystal Interface
LVCMOS-to-3.3V LVPECL Frequency Synthesizer
8430B-71
Data Sheet
G
ENERAL
D
ESCRIPTION
The 8430B-71 is a general purpose, dual output Crystal/
LVCMOS-to-3.3V Differential LVPECL High Frequency Syn-
thesizer and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The 8430B-71 has a
selectable crystal oscillator interface or LVCMOS TEST_CLK.
The VCO operates at a frequency range of 250MHz to 700MHz.
With the output configured to divide the VCO frequency by
2, output frequency steps as small as 2MHz can be achieved
using a 16MHz crystal or test clock. Output frequencies up
to 700MHz can be programmed using the serial or parallel inter-
faces to the configuration logic. The low jitter and frequency range
of the 8430B-71 make it an ideal clock generator for most clock
tree applications.
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable crystal oscillator interface or LVCMOS TEST_CLK
•
Output frequency up to 700MHz
•
Crystal input frequency range: 12MHz to 27MHz
•
VCO range: 250MHz to 700MHz
•
Parallel or serial interface for programming counter and
output dividers
•
RMS period jitter: 9ps (maximum)
•
Cycle-to-cycle jitter: 25ps (maximum)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Replaces 8430-71
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
VCO_SEL
PU
XTAL_SEL
PU
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL_IN
M4
TEST_CLK
PD
0
M5
1
2
3
4
5
6
7
8
M6
32 31 30 29 28 27 26 25
24
23
22
XTAL_OUT
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M3
M2
M1
M0
XTAL_IN
XTAL_OUT
OSC
1
÷16
M7
M8
N0
N1
N2
ICS8430B-71
21
20
19
18
17
PLL
Phase Detector
V
EE
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
MR
PD
VCO
÷M
÷2
0
÷N
1
FOUT0
nFOUT0
FOUT0
nFOUT0
S_LOAD
PD
S_DATA
PD
S_CLOCK
PD
nP_LOAD
PD
M0:M8
N0:N2
Configuration Interface Logic
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc
1
November 30, 2015
8430B-71 Data Sheet
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The 8430B-71 features a fully integrated PLL and therefore re-
quires no external components for setting the loop bandwidth. A
parallel-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior
to the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 700MHz. The output of the M divider is also applied to
the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the 8430B-71 support two in-
put modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition of
the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial
event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will
automatically occur during power-up. The TEST output is LOW when
operating in the parallel input mode. The relationship between the
VCO frequency, the crystal frequency and the M divider is defined
as follows:
fxtal x 2M
fVCO =
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 16MHz reference are
defined as 125
≤
M
≤
350. The frequency out is defined as follows:
fout = fVCO = fxtal x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide values
are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD
is held HIGH, data at the S_DATA input is passed directly to the M
divider and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state of
the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data clocked into register
Output of M divider
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
©2015 Integrated Device Technology, Inc
2
November 30, 2015
8430B-71 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
Name
1, 2, 3,
M5, M6, M7,
28, 29, 30 M0, M1, M2, M3,
31, 32
M4
4
M8
5, 6
7
8, 16
9
10
11, 12
13
14, 15
N0, N1
N2
V
EE
TEST
V
CC
FOUT1, nFOUT1
V
CCO
FOUT0, nFOUT0
Type
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_
LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C
Pullup Function Table. LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core power supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master reset. When logic HIGH, the internal dividers are
reset causing the true outputs (FOUTx) to go low and the inverted out-
17
MR
Input
Pulldown puts (nFOUTx) to go high. When Logic LOW, the internal dividers and
the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
18
S_CLOCK
Input
Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_
19
S_DATA
Input
Pulldown
CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers. LVCMOS
20
S_LOAD
Input
Pulldown
/ LVTTL interface levels.
21
V
CCA
Power
Analog supply pin.
Selects between the crystal oscillator or test clock as the
22
XTAL_SEL
Input
Pullup PLL reference source. Selects XTAL inputs when HIGH.
Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Pulldown Test clock input. LVCMOS interface levels.
24,
XTAL_OUT,
Crystal oscillator interface. XTAL_IN is the input.
Input
25
XTAL_IN
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded
26
nP_LOAD
Input
Pulldown into the M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
27
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
©2015 Integrated Device Technology, Inc
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November 30, 2015
8430B-71 Data Sheet
T
ABLE
3A. P
ARALLEL AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
Conditions
NOTE: L = LOW
H = HIGH
X = Don’t care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
250
252
254
256
•
•
696
698
M Divide
125
126
127
128
•
•
348
349
256
M8
0
0
0
0
•
•
1
1
128
M7
0
0
0
1
•
•
0
0
64
M6
1
1
1
0
•
•
1
1
32
M5
1
1
1
0
•
•
0
0
16
M4
1
1
1
0
•
•
1
1
8
M3
1
1
1
0
•
•
1
1
4
M2
1
1
1
0
•
•
1
1
2
M1
0
1
1
0
•
•
0
0
1
M0
1
0
1
0
•
•
0
1
700
350
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 16MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider Value
2
4
8
16
1
2
4
8
FOUT0, nFOUT0 Output Frequency
(MHz)
Minimum
Maximum
125
350
62.5
31.25
15.625
250
125
62.5
31.25
175
87.5
43.75
700
350
175
87.5
©2015 Integrated Device Technology, Inc
4
November 30, 2015
8430B-71 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
140
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
Parameter
TEST_CLK; NOTE 1
V
IH
V
IL
I
IH
Input
High Voltage
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD, MR,
M0:M8, N0:N2, XTAL_SEL
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
M8, N2, XTAL_SEL, VCO_SEL
TEST_CLK
Input
Low Current
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
TEST_CLK, M8, N2, XTAL_SEL,
VCO_SEL
Test Conditions
Minimum Typical
2.35
2
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
2.6
0.5
Maximum Units
V
CC
+ 0.3
V
CC
+ 0.3
0.8
150
5
200
V
V
V
µA
µA
µA
µA
µA
V
V
Input Low Voltage
Input
High Current
I
IL
V
OH
Output
TEST; NOTE 2
High Voltage
Output
V
OL
TEST; NOTE 2
Low Voltage
NOTE 1: Characterized with 1ns input edge rate.
NOTE 2: Outputs terminated with 50Ω to V
CCO
/2.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50W to V
CCO
- 2V. See “Parameter Measurement Information” section,
“3.3V Output Load Test Circuit” figure.
©2015 Integrated Device Technology, Inc
5
November 30, 2015
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