FemtoClock
®
Crystal-to-3.3V
LVPECL Frequency Synthesizer
843004-125
Data Sheet
G
ENERAL
D
ESCRIPTION
T h e 8 4 3 0 0 4 - 1 2 5 i s a 4 o u t p u t LV P E C L S y n -
t h e s i z e r o p t i m i z e d t o g e n e r a t e E t h e r n e t r e fe r e n c e
clock frequencies and is a member of the family of high
performance clock solutions from IDT. The 843004-125 uses
IDT’s 3
rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet
jitter requirements. The 843004-125 is packaged in a small 24-pin
TSSOP package.
F
EATURES
• Four 3.3V LVPECL output pairs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Crystal oscillator designed for 25MHz, 18pF parallel resonant
crystal
• Supports the following output frequency: 125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.58ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
M Divider Value
25
N Divider Value
5
M/N Divider Value
5
Output Frequency (MHz)
(25MHz Ref.)
125
B
LOCK
D
IAGRAM
Q0
nPLL_SEL
Pulldown
P
IN
A
SSIGNMENT
nQ0
Q1
nQ1
Q1
V
CC
o
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
nc
V
CC
nc
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
V
CC
nXTAL_SEL
REF_CLK
V
EE
XTAL_IN
XTAL_OUT
REF_CLK
Pulldown
25MHz
1
1
nQ1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
÷5
0
Q2
nQ2
Q3
M = 25 (fixed)
nQ3
843004-125
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
MR
Pulldown
©2016 Integrated Device Technology, Inc
1
January 18, 2016
843004-125 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
Name
nQ1, Q1
V
CCO
Q0, nQ0
MR
Power
Ouput
Input
Type
Output
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
the true outputs Qx to go low and the inverted outputs nQx to go high. When logic
Pulldown
LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects
Pulldown PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVC-
MOS/LVTTL interface levels.
No connect.
Analog supply pin.
Core supply pins.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Negative supply pins.
Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between crystal or REF_CLK inputs as the the PLL Reference source. Selects
Pulldown XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
7
8, 10, 12
9
11, 18
13, 14
15, 19
16
17
20, 21
23, 24
Pulldown
nPLL_SEL
nc
V
CCA
V
CC
XTAL_OUT,
XTAL_IN
V
EE
REF_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Power
Input
Power
Input
Input
Output
Output
NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
©2016 Integrated Device Technology, Inc
2
January 18, 2016
843004-125 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
82.3°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.15
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
130
15
Units
V
V
V
mA
mA
Included in I
EE
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
REF_CLK, MR, nPLL_
SEL, nXTAL_SEL
REF_CLK, MR, nPLL_
SEL, nXTAL_SEL
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
VIN
= 0V
-5
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
- 2V.
©2016 Integrated Device Technology, Inc
3
January 18, 2016
843004-125 Data Sheet
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF, parallel resonant crystal.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Ω
pF
Maximum
Units
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
f
OUT
tsk(o)
tjit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 2
RMS Phase Jitter; NOTE 3
Output Rise/Fall Time
Test Conditions
Minimum
112
Typical
125
0.58
Maximum
136
50
Units
MHz
ps
ps
ps
125MHz (1.875MHz - 20MHz)
20% to 80%
300
600
odc
Output Duty Cycle
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditons.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Phase jitter is dependent on the input source used.
©2016 Integrated Device Technology, Inc
4
January 18, 2016
843004-125 Data Sheet
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
N
OISE
P
OWER
dBc
Hz
➤
10Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.58ps (typical)
Raw Phase Noise Data
➤
©2016 Integrated Device Technology, Inc
5
➤
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
January 18, 2016
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