CMOS SyncBiFIFO
TM
256 x 18 x 2 and 512 x 18 x 2
FEATURES:
• Two independent FIFO memories for fully bidirectional data
transfers
• 256 x 18 x 2 organization (IDT72605)
• 512 x 18 x 2 organization (IDT72615)
• Synchronous interface for fast (20ns) read and write cycle times
• Each data port has an independent clock and read/write control
• Output enable is provided on each port as a three-state control
of the data bus
• Built-in bypass path for direct data transfer between two ports
• Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
• Programmable flag offset can be set to any depth in the FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
Quad Flatpack) and 68-pin PLCC
• Industrial temperature range (–40°C to +85°C)
°
°
IDT72605
IDT72615
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power bidirec-
tional First-In, First-Out (FIFO) memories, with synchronous interface for fast
read and write cycle times. The SyncBiFIFO™ is a data buffer that can store
or retrieve information from two sources simultaneously. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Each Port has its own independent clock. Data transfers to the
I/O registers are gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individual output enable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whether those data lines are in a high-impedance state.
Bypass control allows data to be directly transferred from input to output
register in either direction.
The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full,
and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full
and Almost-Empty flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed, submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
D
A0
-D
A17
EN
A
R/W
A
OE
A
HIGH
Z
CONTROL
CLK
A
INPUT REGISTER
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
MUX
MEMORY
ARRAY
512 x 18
256 x 18
RESET
LOGIC
RS
CS
A
A
2
A
1
A
0
EF
AB
PAE
AB
PAF
AB
FF
AB
µP
INTERFACE
FLAG
LOGIC
FLAG
LOGIC
EF
BA
PAE
BA
PAF
BA
FF
BA
3
7
POWER
SUPPLY
INPUT REGISTER
V
CC
GND
CLK
B
OE
B
R/W
B
EN
B
HIGH
Z
CONTROL
OUTPUT REGISTER
BYP
B
The SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
D
B0
-D
B17
2704 drw 01
INDUSTRIAL TEMPERATURE RANGE
1
©
2000 Integrated Device Technology, Inc.
NOVEMBER 2000
DSC-2704/6
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 AND 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
D
A15
GND
D
A14
D
A13
D
A12
D
A11
D
A10
V
CC
GND
D
A9
D
A8
D
A7
D
A6
D
A5
GND
D
A4
D
A3
D
A16
C
A17
CLK
A
R/W
A
EN
A
CS
A
A
0
A
1
A
2
V
CC
EF
AB
FF
AB
PAE
AB
PAF
AB
OE
A
D
B17
D
B16
9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61
1
60
10
59
11
58
12
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D
B15
GND
D
B14
D
B13
D
B12
D
B11
D
B10
V
CC
GND
D
B9
D
B8
D
B7
D
B6
D
B5
GND
D
B4
D
B3
D
A2
D
A1
D
A0
EF
BA
FF
BA
PAE
BA
PAF
BA
GND
BYP
B
OE
B
EN
B
R/W
B
CLK
B
RS
D
B0
D
B1
D
B2
2704 drw 02
PLCC (J68-1, order code: J)
TOP VIEW
PIN 1
D
A2
D
A3
D
A4
D
A5
D
A6
D
A7
D
A8
D
A9
GND
V
CC
D
A10
D
A11
D
A12
D
A13
D
A14
D
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D
B3
D
B4
GND
D
B5
D
B6
D
B7
D
B8
D
B9
D
B10
D
B11
D
B12
D
B13
D
B14
GND
D
B15
D
B16
D
A16
D
A17
CLK
A
R/W
A
EN
A
CS
A
A
0
A
1
A
2
V
CC
EF
AB
FF
AB
PAE
AB
PAF
AB
OE
A
D
B17
D
A1
D
A0
EF
BA
FF
BA
PAE
BA
PAF
BA
GND
BYB
B
OE
B
EN
B
R/W
B
CLK
B
RS
D
B0
D
B1
D
B2
2704 drw 03
TQFP (PN64-1, order code: PF)
TOP VIEW
2
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 AND 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D
A0
-D
A17
CS
A
R/W
A
Name
Data A
Chip Select A
Read/Write A
I/O
I/O
I
I
Description
Data inputs & outputs for the 18-bit Port A bus.
Port A is accessed when
CS
A
is LOW. Port A is inactive if
CS
A
is HIGH.
This pin controls the read or write direction of Port A. If R/W
A
is LOW, Data A input data is written into Port A. If R/W
A
is HIGH,
Data A output data is read from Port A. In bypass mode, when R/W
A
is LOW, message is written into A→B output register. If
R/W
A
is HIGH, message is read from B→A output register.
CLK
A
is typically a free running clock. Data is read or written into Port A on the rising edge of CLK
A
.
When
EN
A
is LOW, data can be read or written to Port A. When
EN
A
is HIGH, no data transfers occur.
When R/W
A
is HIGH, Port A is an output bus and
OE
A
controls the high-impedance state of D
A0
-D
A17
. If
OE
A
is HIGH, Port A is
in a high-impedance state. If
OE
A
is LOW while
CS
A
is LOW and R/W
A
is HIGH, Port A is in an active (low-impedance) state.
When
CS
A
is asserted, A
0
, A
1
, A
2
and R/W
A
are used to select one of six internal resources.
Data inputs & outputs for the 18-bit Port B bus.
This pin controls the read or write direction of Port B. If R/W
B
is LOW, Data B input data is written into Port B. If R/W
B
is HIGH,
Data B output data is read from Port B. In bypass mode, when R/W
B
is LOW, message is written into B→A output register. If
R/W
B
is HIGH, message is read from A→B output register.
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLK
B
.
When
EN
B
is LOW, data can be read or written to Port B. When
EN
B
is HIGH, no data transfers occur.
When R/W
B
is HIGH, Port B is an output bus and
OE
B
controls the high-impedance state of D
B0
-D
B17
. If OE
B
is HIGH, Port B is
in a high-impedance state. If
OE
B
is LOW while R/W
B
is HIGH, Port B is in an active (low-impedance) state.
When
EF
AB
is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited. When
EF
AB
is HIGH, the FIFO is
not empty.
EF
AB
is synchronized to CLK
B
. In the bypass mode,
EF
AB
HIGH indicates that data D
A0
-D
A17
is available for passing
through. After the data D
B0
-D
B17
has been read,
EF
AB
goes LOW.
When
PAE
AB
is LOW, the A→B FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
programmed into
PAE
AB
Register. When
PAE
AB
is HIGH, the A→B FIFO contains more than offset in
PAE
AB
Register. The
default offset value for
PAE
AB
Register is 8.
PAE
AB
is synchronized to CLK
B
.
When
PAF
AB
is LOW, the A→B FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset
programmed into
PAF
AB
Register. When
PAF
AB
is HIGH, the A→B FIFO contains less than or equal to the depth minus the
offset in
PAF
AB
Register. The default offset value for
PAF
AB
Register is 8.
PAF
AB
is synchronized to CLK
A
.
When
FF
AB
is LOW, the A→B FIFO is full and further data writes into Port A are inhibited. When
FF
AB
is HIGH, the FIFO is not
full.
FF
AB
is synchronized to CLK
A
. In bypass mode,
FF
AB
tells Port A that a message is waiting in Port B’s output register. If
FF
AB
is LOW, a bypass message is in the register. If
FF
AB
is HIGH, Port B has read the message and another message can be
written into Port A.
When
EF
BA
is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited. When
EF
BA
is HIGH, the FIFO
is not empty.
EF
BA
is synchronized to CLK
A
. In the bypass mode,
EF
BA
HIGH indicates that data D
B0
-D
B17
is available for
passing through. After the data D
A0
-D
A17
has been read,
EF
BA
goes LOW on the following cycle.
When
PAE
BA
is LOW, the B→A FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
programmed into
PAE
BA
Register. When
PAE
BA
is HIGH, the B→A FIFO contains more than offset in
PAE
BA
Register. The
default offset value for
PAE
BA
Register is 8.
PAE
BA
is synchronized to CLK
A
.
When
PAF
BA
is LOW, the B→A FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset
programmed into
PAF
BA
Register. When
PAF
BA
is HIGH, the B→A FIFO contains less than or equal to the depth minus the
offset in
PAF
BA
Register. The default offset value for
PAF
BA
Register is 8.
PAF
BA
is synchronized to CLK
B
.
When
FF
BA
is LOW, the B→A FIFO is full and further data writes into Port B are inhibited. When
FF
BA
is HIGH, the FIFO is
not full.
FF
BA
is synchronized to CLK
B
. In bypass mode,
FF
BA
tells Port B that a message is waiting in Port A’s output register. If
FF
BA
is LOW, a bypass message is in the register. If
FF
BA
is HIGH, Port A has read the message and another message can be
written into Port B.
This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYP
B
is LOW, Port A has placed the FIFO into
bypass mode. If
BYP
B
is HIGH, the synchronous BiFIFO passes data into memory.
BYP
B
is synchronized to CLK
B
.
A LOW on this pin will perform a reset of all synchronous BiFIFO functions.
There are three +5V power pins for the PLCC and two for the TQFP.
There are seven ground pins for the PLCC and four for the TQFP.
CLK
A
EN
A
OE
A
Clock A
Enable A
Output Enable A
I
I
I
I
I/O
I
A
0
, A
1
, A
2
Addresses
D
B0
-D
B17
Data B
Read/Write B
R/W
B
CLK
B
EN
B
OE
B
EF
AB
Clock B
Enable B
Output Enable B
A→B Empty
Flag
A→B
Programmable
Almost-Empty
Flag
A→B
Programmable
Almost-Full
Flag
A→B Full Flag
I
I
I
O
PAE
AB
O
PAF
AB
O
FF
AB
O
EF
BA
B→A Empty
Flag
B→A
Programmable
Almost-Empty
Flag
B→A
Programmable
Almost-Full
Flag
B→A Full Flag
O
PAE
BA
O
PAF
BA
O
FF
BA
O
BYP
B
RS
V
CC
GND
Port B Bypass
Flag
Reset
Power
Ground
O
I
3
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 AND 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to Ground
Storage Temperature
DC Output Current
Industrial
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
SYMBOL
V
CC
GND
V
IH
V
IL
(1)
T
A
PARAMETER
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
MIN. TYP. MAX. UNIT
4.5
0
2.0
—
-40
5.0
0
—
—
—
5.5
0
—
0.8
85
V
V
V
V
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
(Industrial: V
CC
= 5V ± 10%, T
A
= -40
°
C to +85
°
C)
DC ELECTRICAL CHARACTERISTICS
IDT72615L
IDT72605L
Industrial
t
CLK
= 20, 25, 35, 50ns
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC
(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic "1" Voltage I
OUT
= –2mA
Output Logic "0" Voltage I
OUT
= 8mA
Active Power Supply Current
Min.
–1
–10
2.4
—
—
Typ.
—
—
—
—
—
Max.
1
10
—
0.4
230
Unit
µA
µA
V
V
mA
NOTES:
1. Measurements with 0.4V
≤
V
IN
≤
V
CC
.
2.
OEA, OEB
≥
V
IH
; 0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs open (I
OUT
= 0). Testing frequency f=20MHz.
CAPACITANCE
(T
A
= +25
°
C, F = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
4
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 AND 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 2
+5V
1.1KΩ
D.U.T.
680Ω
30pF*
2704 drw 04
or equivalent circuit
Figure 2. Output Load
* Includes jig and scope capacitances.
AC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5V ± 10%, T
A
= -40°C to +85°C)
IDT72615L20
IDT72605L20
Min.
Max.
—
50
20
8
8
20
12
12
—
3
6
1
6
1
3
0
3
—
—
—
—
10
17
—
—
—
—
—
—
27
10
—
—
—
—
10
—
10
10
10
12
12
—
—
Industrial
IDT72615L25
IDT72615L35
IDT72605L25
IDT72605L35
Min.
Max.
Min.
Max.
—
40
—
28
25
10
10
25
15
15
—
3
6
1
6
1
3
0
3
—
—
—
—
12
19
—
—
—
—
—
—
28
15
—
—
—
—
13
—
13
15
15
15
15
—
—
35
14
14
35
21
21
—
3
8
1
8
1
3
0
3
—
—
—
—
17
25
—
—
—
—
—
—
35
21
—
—
—
—
20
—
20
21
21
21
21
—
—
IDT72615L50
IDT72605L50
Min.
Max.
—
20
50
20
20
50
30
30
—
3
10
1
10
1
3
0
3
—
—
—
—
20
34
—
—
—
—
—
—
50
25
—
—
—
—
28
—
28
30
30
30
30
—
—
Symbol
Parameter
f
CLK
Clock frequency
t
CLK
t
CLKH
t
CLKL
t
RS
t
RSS
t
RSR
t
RSF
t
A
t
CS
t
CH
t
DS
t
DH
t
OE
t
OLZ
t
OHZ
t
FF
t
EF
t
PAE
t
PAF
t
SKEW1
t
SKEW2
Clock cycle time
Clock HIGH time
Clock LOW time
Reset pulse width
Reset setup time
Reset recovery time
Reset to flags in initial state
Data access time
Control signal setup time
(1)
Control signal hold time
(1)
Data setup time
Data hold time
Output Enable LOW to output data valid
(2)
Output Enable LOW to data bus at Low-Z
(2)
Output Enable HIGH to data bus at High-Z
(2)
Clock to Full Flag time
Clock to Empty Flag time
Clock to Programmable
Almost-Empty Flag time
Clock to Programmable
Almost-Full Flag time
Skew between CLK
A
& CLK
B
for Empty/Full Flags
(2)
Skew between CLK
A
& CLK
B
for Programmable Flags
(2)
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing Figures
—
4,5,6,7
4,5,6,7,12,13,14,15
4,5,6,7,12,13,14,15
3
3
3
3
5,7,8,9,10,11
4,5,6,7,8,9,10,11,
12, 13,14,15
4,5,6,7,10,11,12,
13, 14,15
4,6,8,9,10,11
4,6
5,7,8,9,10,11
5,7,8,9,10,11
5,7,10,11
4,6,10,11
5,7,8,9,10,11
12,14
13,15
4,5,6,7,8,9,10,11
4, 7,12,13,14,15
NOTES:
1. Control signals refer to
CS
A
, R/W
A
,
EN
A
, A
2
, A
1
, A
0
, R/W
B
,
EN
B
.
2. Minimum values are guaranteed by design.
5
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