74AC16374
16-BIT D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS (NON INVERTED)
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 120MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 8µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50Ω TRASMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
IMPROVED LATCH-UP IMMUNITY
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74AC16374TTR
DESCRIPTION
The 74AC16374 is an advanced high-speed
CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS tecnology.
This 16 bit D-Type Flip-Flop is controlled by two
clock inputs (CK) and two output enable inputs
(OE). The device can be used as two 8-bit
flip-flops or one 16-bit flip-flop.
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the outputs will be in
a normal logic state (high or low logic level); while
OE is high, the outputs will be in a high impedance
state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION
February 2003
1/10
74AC16374
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 3, 5, 6, 8, 9,
11, 12
13, 14, 16, 17,
19, 20, 22, 23
24
SYMBOL
1OE
1Q0 to
1Q7
2Q0 to
2Q7
2OE
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
3-State Outputs
3-State Outputs
IEC LOGIC SYMBOLS
3 State Output Enable
Input (Active LOW)
25
2CK
Clock Input (LOW-to-HIGH
Edge Trigger)
36, 35, 33, 32, 2D0 to 2D7 Data Inputs
30, 29, 27, 26
47, 46, 44, 43, 1D0 to 1D7 Data Inputs
41, 40, 38, 37
48
1CK
Clock Input (LOW-to-HIGH
Edge Trigger)
4, 10, 15, 21,
GND
Ground (0V)
28, 34, 39, 45
7, 18, 31, 42
V
CC
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE
H
L
L
L
X : Don’t Care
Z : High Impedance
OUTPUTS
D
X
X
L
H
Q
Z
NO CHANGE
L
H
CK
X
2/10
74AC16374
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0, 4.5 or 5.5V (note 1)
Parameter
Value
2 to 6
0 to V
CC
0 to V
CC
-55 to 125
8
Unit
V
V
V
°C
ns/V
1) V
IN
from 30% to 70% of V
CC
3/10
74AC16374
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
2.5
2.5
1.5
2.0
1.0
1.0
60
100
T
A
= 25 °C
Min.
Typ.
5.9
4.2
6.7
4.9
6.3
4.9
2.0
2.0
1.0
1.2
-0.5
-0.5
100
120
Max.
9.8
6.5
11.1
7.3
10.0
7.6
5.2
4.2
2.5
2.5
1.5
1.5
60
100
Value
-40 to 85 °C -55 to 125°C
Min.
Max.
17.0
10.8
21.2
12.1
12.0
9.1
5.2
4.2
2.5
2.5
1.5
1.5
60
100
ns
Min.
Max.
17.0
10.8
21.2
12.1
12.0
9.1
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
CK to Q
t
PZL
t
PZH
Output Enable
Time
t
PLZ
t
PHZ
Output Disable
Time
t
W
CLOCK Pulse
Width HIGH or
LOW
Setup Time D to
CK, HIGH or LOW
Hold Time D to CK,
HIGH or LOW
Maximum Clock
Frequency
ns
ns
t
s
t
h
f
MAX
ns
ns
MHz
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25 °C
Min.
C
IN
C
OUT
C
PD
Input Capacitance
Output Capaci-
tance
Power Dissipation
Capacitance (note
1)
5.0
5.0
5.0
f
IN
=10MHz
Typ.
3.5
11
20
Max.
Value
-40 to 85 °C -55 to 125°C
Min.
Max.
Min.
Max.
pF
pF
pF
Unit
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
5/10
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