HIGH-SPEED 3.3V 256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
x
PRELIMINARY
IDT70V631S
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V631 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
UB
L
LB
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
UB
R
LB
R
R/W
L
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
R/W
R
CE
0 L
CE
1 L
CE
0 R
CE
1 R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
256K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
A
17L
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
17R
A
0R
OE
L
CE
0L
CE
1L
R/W
L
BUSY
L
SEM
L
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
CE
0 R
CE
1 R
R/W
R
BUSY
R
M/S
SEM
R
INT
R
TDI
TDO
JTAG
TMS
TCK
TRST
5622 drw 01
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
AUGUST 2001
DSC-5622/4
1
©2001 Integrated Device Technology, Inc.
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description
The IDT70V631 is a high-speed 256K x 18 Asynchronous Dual-Port
Static RAM. The IDT70V631 is designed to be used as a stand-alone
4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 36-bit-or-more word system. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 36-bit or wider memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either
CE
0
or CE
1
) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The 70V631 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (V
DD
) remains at 3.3V.
Pin Configurations
(1,2,3,4)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
2
NC
3
V
SS
4
TDO
5
NC
6
A
16L
7
A
12L
8
A
8L
9
NC
10 11
V
DD
SEM
L
12
INT
L
13 14
A
4L
A
0L
15
OPT
L
16 17
NC
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
V
SS
NC
TDI
A
17 L
A
13L
A
9L
NC
CE
0L
V
SS
BUSY
L
A
5L
A
1L
V
SS
V
DDQR
I/O
8L
NC
V
DDQL
I/O
9R
V
DDQR
V
DD
NC
A
14L
A
10L
UB
L
CE
1L
V
SS
R /
W
L
A
6L
A
2L
V
DD
I/O
8R
NC
V
SS
NC
V
SS
I/O
10L
NC
A
15L
A
11 L
A
7L
LB
L
V
DD
OE
L
NC
A
3L
V
DD
NC
V
DDQL
I/O
7L
I/O
7R
I/O
11L
NC
V
DDQR
I/O
10R
I/O
6L
NC
V
SS
NC
V
DDQL
I/O
11R
NC
V
SS
V
SS
I/O
6R
NC
V
DDQR
NC
V
SS
I/O
12L
NC
NC
V
DDQL
I/O
5L
NC
V
DD
NC
V
DDQR
I/O
12R
70V631BF
BF-208
(5)
208-Ball BGA
Top View
(6)
V
DD
NC
V
SS
I/O
5R
V
DDQL
V
DD
V
SS
V
SS
V
SS
V
DD
V
SS
V
DDQR
I/O
14R
V
SS
I/O
13R
V
SS
I/O
3R
V
DDQL
I/O
4R
V
SS
NC
I/O
14L
V
DDQR
I/O
13L
NC
I/O
3L
V
SS
I/O
4L
V
DDQL
NC
I/O
15R
V
SS
V
SS
NC
I/O
2R
V
DDQR
NC
V
SS
NC
I/O
15L
I/O
1R
V
DDQL
NC
I/O
2L
I/O
16R
I/O
16L
V
DDQR
NC
TRST
A
16R
A
12R
A
8R
NC
V
DD
SEM
R
INT
R
A
4R
NC
I/O
1L
V
SS
NC
V
SS
NC
I/O
17R
TCK
A
17R
A
13R
A
9R
NC
CE
0R
V
SS
BUSY
R
A
5R
A
1R
V
SS
V
DDQL
I/O
0R
V
DDQR
NC
I/O
17L
V
DDQL
TMS
NC
A
14R
A
10R
UB
R
CE
1R
V
SS
R/W
R
A
6R
A
2R
V
SS
NC
V
SS
NC
V
SS
NC
V
DD
NC
A
15R
A
11R
A
7R
LB
R
V
DD
OE
R
M/S
A
3R
A
0R
V
DD
OPT
R
NC
I/O
0 L
5622 tbl 02b
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V) and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4,7)
(con't.)
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
UB
L
LB
L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
SEM
L
OE
L
R/W
L
BUSY
L
INT
L
NC
A
6L
A
5L
A
4L
A
3L
A
2L
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
A
14L
A
15L
A
16L
A
17L
IO
9L
IO
9R
V
DDQL
V
SS
IO
10L
IO
10R
V
DDQR
V
SS
IO
11L
IO
11R
IO
12L
IO
12R
V
DD
V
DD
V
SS
V
SS
IO
13R
IO
13L
IO
14R
IO
14L
IO
15R
IO
15L
V
DDQL
V
SS
IO
16R
IO
16L
V
DDQR
V
SS
IO
17R
IO
17L
A
17R
A
16R
A
15R
A
14R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V631PRF
PK-128
(5)
128-Pin TQFP
Top View
(6)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A
1L
A
0L
OPT
L
V
SS
IO
8L
IO
8R
NC
V
SS
V
DDQL
IO
7L
IO
7R
V
SS
V
DDQR
IO
6L
IO
6R
IO
5L
IO
5R
V
DD
V
DD
V
SS
V
SS
IO
4R
IO
4L
IO
3R
IO
3L
IO
2R
IO
2L
V
SS
V
DDQL
IO
1R
IO
1L
V
SS
V
DDQR
IO
0R
IO
0L
OPT
R
A
0R
A
1R
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
.
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
UB
R
LB
R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
SEM
R
OE
R
R/W
R
BUSY
R
INT
R
M/S
A
6R
A
5R
A
4R
A
3R
A
2R
5622 drw 02a
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V) and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. Due to the restricted number of pins, JTAG is not supported in the PK-128 package.
3
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
70V631BC
BC-256
(5)
256-Pin BGA
Top View
(6)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
B1
TDI
B2
NC
B3
A
17L
B4
A
14L
B5
A
11L
B6
A
8L
B7
NC
B8
CE
1L
B9
OE
L
B10
INT
L
B11
A
5L
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
NC
C1
NC
C2
TDO
C3
NC
C4
A
15L
C5
A
12L
C6
A
9L
C7
UB
L
C8
CE
0L
R/W
L
C9
C10
NC
C11
A
4L
C12
A
1L
C13
NC
C14
NC
C15
NC
C16
NC
D1
I/O
9L
D2
V
SS
D3
A
16L
D4
A
13L
D5
A
10L
D6
A
7L
D7
NC
D8
LB
L
D9
SEM
L
BUSY
L
D10
D11
A
6L
D12
A
3L
D13
OPT
L
D14
NC
D15
I/O
8L
D16
NC
E1
I/O
9R
E2
NC
E3
V
DD
E4
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E5
E6
E7
E8
E9
E10
E11
E12
E13
NC
E14
NC
E15
I/O
8R
E16
I/O
10R
I/O
10L
F1
F2
NC
F3
V
DDQL
F4
V
DD
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
F12
F13
NC
F14
I/O
7L
F15
I/O
7R
F16
I/O
11L
G1
NC
G2
I/O
11R
V
DDQL
G3
G4
V
DD
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
V
DDQR
I/O
6R
G12
G13
G14
NC
G15
I/O
6L
G16
NC
H1
NC
H2
I/O
12L
V
DDQR
H3
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
H13
I/O
5L
H14
NC
H15
NC
H16
NC
J1
I/O
12R
J2
NC
J3
V
DDQR
V
SS
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
J13
NC
J14
NC
J15
I/O
5R
J16
I/O
13L
I/O
14R
I/O
13R
V
DDQL
K1
K2
K3
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
DDQR
I/O
4R
I/O
3R
K13
K14
K15
I/O
4L
K16
NC
L1
NC
L2
I/O
14L
V
DDQL
L3
L4
V
SS
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
L13
NC
L14
NC
L15
I/O
3L
L16
I/O
15L
M1
NC
M2
I/O
15R
V
DDQR
M3
M4
V
DD
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
2L
M13
M14
NC
M15
I/O
2R
M16
I/O
16R
I/O
16L
N1
N2
NC
N3
V
DDQR
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
1R
N13
N14
I/O
1L
N15
NC
N16
NC
P1
I/O
17R
P2
NC
P3
V
DD
P4
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P5
P6
P7
P8
P9
P10
P11
P12
V
DD
P13
NC
P14
I/O
0R
P15
NC
P16
NC
R1
I/O
17L
TMS
R2
R3
A
16R
R4
A
13R
R5
A
10R
R6
A
7R
R7
NC
R8
LB
R
R9
SEM
R
BUSY
R
R10
R11
A
6R
R12
A
3R
R13
NC
R14
NC
R15
I/O
0L
R16
NC
T1
NC
T2
TRST
T3
NC
T4
A
15R
T5
A
12R
T6
A
9R
T7
UB
R
T8
CE
0R
R/W
R
T9
T10
M/S
T11
A
4R
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
TCK
NC
A
17R
A
14R
A
11R
A
8R
NC
CE
1R
OE
R
INT
R
A
5R
A
2R
A
0R
NC
NC
5622 drw 02c
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
,
4
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
17L
I/O
0L
- I/O
17L
SEM
L
INT
L
BUSY
L
UB
L
LB
L
V
DDQL
OPT
L
M/S
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
17R
I/O
0R
- I/O
17R
SEM
R
INT
R
BUSY
R
UB
R
LB
R
V
DDQR
OPT
R
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Upper Byte Select
Lower Byte Select
Power (I/O Bus) (3.3V or 2.5V)
(1)
Option for selecting V
DDQX
(1,2)
Master or Slave Select
Power (3.3V)
(1)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5622 tbl 01
Names
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on I/O
X
.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to V
IH
(3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to V
IL
(0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX
must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
5
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