22V10
PALCE22V10
Flash Erasable,
Reprogrammable CMOS PAL® Device
Features
•
Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
•
CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
•
Variable product terms
— 2 x(8 through 16) product terms
•
User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
•
Up to 22 input terms and 10 outputs
•
DIP, LCC, and PLCC available
— 5 ns commercial version
4 ns t
CO
3 ns t
S
5 ns t
PD
181-MHz state machine
— 10 ns military and industrial versions
7 ns t
CO
6 ns t
S
10 ns t
PD
110-MHz state machine
— 15-ns commercial, industrial, and military versions
— 25-ns commercial, industrial, and military versions
•
High reliability
— Proven Flash EPROM technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE22V10 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-products (AND-OR) logic
structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
V
SS
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
CP/I
1
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
I
14
I/O9
15
I/O8
16
I/O 7
17
I/O6
18
I/O5
19
I/O4
20
I/O3
21
I/O2
22
I/O1
23
I/O0
24
V
CC
CE22V10–1
Pin Configuration
I
I
CP/I
NC
V
CC
I/O0
I/O1
4 3 2 1 282726
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
12131415161718
V
SS
NC
I/O9
I/O8
CE22V10–2
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
I
I
CP/I
NC
V
CC
I/O0
I/O1
4 3 2 1 2827 26
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
CE22V10–3
121314 1516 1718
V
SS
NC
LCC
Top View
PLCC
Top View
PAL is a registered trademark of Advanced Micro Devices.
Cypress Semiconductor Corporation
Document #: 38-03027 Rev. **
•
3901 North First Street
•
San Jose
I/O9
I/O8
I
I
I
I
I
I
•
CA 95134 • 408-943-2600
Revised September 1996
PALCE22V10
Selection Guide
t
PD
ns
Generic Part Number
PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25
Com’l
5
7.5
10
15
25
10
15
25
Mil/Ind
3
5
6
10
15
6
10
15
t
S
ns
Com’l
Mil/Ind
4
5
7
8
15
7
8
15
t
CO
ns
Com’l
Mil/Ind
I
CC
mA
Com’l
130
130
90
90
90
150
120
120
Mil/Ind
Functional Description
(continued)
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and provides
up to 22 inputs and 10 outputs. The PALCE22V10 can be elec-
trically erased and reprogrammed. The programmable macro-
cell provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually selected, allowing complete
flexibility of output configuration. Further configurability is pro-
vided through “array” configurable “output enable” for each po-
tential output. This feature allows the 10 outputs to be recon-
figured as inputs on an individual basis, or alternately used as
a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized to the configurations found in a majority of
applications without creating devices that burden the product
term structures with unusable product terms and lower perfor-
mance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminat-
ing the need to dedicate standard product terms for initializa-
tion functions. The device automatically resets upon pow-
er-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array com-
plexity. Since each of the 10 output pins may be individually
configured as inputs on a temporary or permanent basis, func-
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten-
tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en-
abled as an output and an input through the selective use of
individual product terms associated with each output. Each of
these outputs is achieved through an individual programmable
macrocell. These macrocells are programmable to provide a
combinatorial or registered inverting or non-inverting output. In
a registered mode of operation, the output of the register is fed
back into the array, providing current status information to the
array. This information is available for establishing the next
result in applications such as control state machines. In a com-
binatorial configuration, the combinatorial output or, if the out-
put is disabled, the signal present on the I/O pin is made avail-
able to the array. The flexibility provided by both
programmable product term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash re-
programmability.
Configuration Table
Registered/Combinatorial
C
1
0
0
1
1
C
0
0
1
0
1
Configuration
Registered/Active LOW
Registered/Active HIGH
Combinatorial/Active LOW
Combinatorial/Active HIGH
Document #: 38-03027 Rev. **
Page 2 of 13
PALCE22V10
Macrocell
AR
OUTPUT
SELECT
MUX
D
Q
CP
Q
S
1
S
0
SP
INPUT/
FEEDBACK
MUX
S
1
C
1
C
0
MACROCELL
CE22V10–4
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW) .............................16 mA
Note:
1. T
A
is the “instant on” case temperature.
DC Programming Voltage............................................. 12.5V
Latch-Up Current..................................................... >200 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2001V
Operating Range
Range
Commercial
Industrial
Military
[1]
Ambient
Temperature
0
°
C to +75
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V
±5%
5V
±10%
5V
±10%
Document #: 38-03027 Rev. **
Page 3 of 13
PALCE22V10
]
Electrical Characteristics
Over the Operating Range
[2]
Parameter
V
OH
V
OL
V
IH
V
IL[4]
I
IX
I
OZ
I
SC
I
CC1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Leakage Current
Output Leakage Current
Standby Power Supply
Current
V
CC
= Min.,
V
IN
= V
IH
or V
IL
V
CC
= Min.,
V
IN
= V
IH
or V
IL
Test Conditions
I
OH
= –3.2 mA
I
OH
= –2 mA
I
OL
= 16 mA
I
OL
= 12 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
2.0
–0.5
–10
–40
–30
Com’l
Mil/Ind
Com’l
Com’l
Mil/Ind
Mil/Ind
0.8
10
40
–130
90
130
120
120
110
140
130
130
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
[3]
Min.
2.4
Max.
Unit
V
0.5
V
Guaranteed Input Logical HIGH Voltage for All Inputs
[3]
Guaranteed Input Logical LOW Voltage for All Inputs
V
SS
< V
IN
< V
CC
, V
CC
= Max.
V
CC
= Max., V
SS
< V
OUT
< V
CC
V
CC
= Max.,
V
IN
= GND,
Outputs Open in
Unprogrammed
Device
V
CC
= Max., V
IL
=
0V, V
IH
= 3V,
Output Open, De-
vice Programmed
as a 10-Bit
Counter,
f = 25 MHz
10, 15, 25 ns
5, 7.5 ns
15, 25 ns
10 ns
10, 15, 25 ns
5, 7.5 ns
15, 25 ns
10 ns
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[5,6]
I
CC2[6]
Operating Power Supply
Current
Capacitance
[6]
Parameter
C
IN
C
OUT
]
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2.0V @ f = 1 MHz
V
OUT
= 2.0V @ f = 1 MHz
Min.
Max.
10
10
Unit
pF
pF
Endurance Characteristics
[6]
Parameter
N
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Min.
100
Max.
Unit
Cycles
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. V
IL
(Min.) is equal to -3.0V for pulse durations less than 20 ns.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03027 Rev. **
Page 4 of 13
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