NB6L14
2.5 V/3.3 V 3.0 GHz
Differential 1:4 LVPECL
Fanout Buffer
Multi−Level Inputs with Internal Termination
Description
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MARKING
DIAGRAM*
1
QFN−16
MN SUFFIX
CASE 485G
16
NB6L
14
ALYWG
G
The NB6L14 is a 3.0 GHz differential 1:4 LVPECL clock or data
fanout buffer. The differential inputs incorporate internal 50
W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L14 to accept various logic standards, such as
LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The
VREF_AC reference output can be used to rebias capacitor−coupled
differential or single−ended input signals. The 1:4 fanout design was
optimized for low output skew applications.
The NB6L14 is a member of the ECLinPS MAX™ family of high
performance clock and data management products.
Features
1
•
•
•
•
•
•
•
•
•
•
•
•
Input Clock Frequency > 3.0 GHz
Input Data Rate > 2.5 Gb/s
< 20 ps Within Device Output Skew
350 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 700 mV Amplitude, Typical
LVPECL Mode Operating Range: V
CC
= 2.375 V to 3.63 V with
GND = 0 V
Internal 50
W
Input Termination Resistors Provided
VREF_AC Reference Output Voltage
−40°C
to +85°C Ambient Operating Temperature
Available in 3 mm x 3 mm 16 Pin QFN
These are Pb−Free Devices
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
Q1
IN
VT
IN
Q2
Q1
EN
VREFAC
D
Q
Q2
Q3
Q3
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
May, 2012
−
Rev. 5
1
Publication Order Number:
NB6L14/D
NB6L14
Q0
Q0
16
Q1
Q1
Q2
Q2
1
2
3
4
5
Q3
6
Q3
7
V
CC
8
EN
Q0
15
V
CC
GND
14
13
12 IN
11 VT
10 VREF_AC
9
IN
IN
50
W
VT
50
W
/IN
Exposed Pad (EP)
/Q0
Q1
/Q1
Q2
EN
VREF_AC
D
Q
CLK
/Q2
Q3
/Q3
Figure 2. QFN−16 Pinout
(Top View)
Table 1. EN TRUTH TABLE
IN
0
1
x
IN
1
0
x
EN
1
1
0
Q0:Q3
0
1
0+
Figure 3. Logic Diagram
Q0:Q3
1
0
1+
+ = On next negative transition of the input signal (IN).
x = Don’t care.
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
Name
Q1
Q1
Q2
Q2
Q3
Q3
V
CC
EN
I/O
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
−
LVTTL/LVCMOS
Description
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to
V
CC
–2.0 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to
V
CC
– 2.0 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to
V
CC
– 2.0 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
– 2.0 V.
Positive Supply Voltage
Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal DFF register is
clocked on the falling edge of IN input (see Figure 20). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
Inverted Differential Clock Input. Internal 50
W
Resistor to Termination Pin, VT.
Output Voltage Reference for capacitor−coupled inputs, only.
Internal 100
W
center−tapped Termination Pin for IN and IN.
LVPECL, CML,
LVDS, HSTL
−
−
LVPECL Output
LVPECL Output
−
Non−inverted Differential Clock Input. Internal 50
W
Resistor to Termination Pin, VT.
Negative Supply Voltage
Positive Supply Voltage
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to
V
CC
–2.0 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
–2.0 V.
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat−sinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
9
10
11
12
13
14
15
16
−
IN
VREF_AC
VT
IN
GND
V
CC
Q0
Q0
EP
LVPECL, CML,
LVDS, HSTL
1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN inputs, then the device will be susceptible to self−oscillation.
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NB6L14
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN−16
Oxygen Index: 28 to 34
Value
> 4 kV
> 100 V
Level 1
UL 94 V−0 @ 0.125 in
167
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
Io
I
IN
I
VREF_AC
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input/Output
Input Current
Source or Sink Current (IN/IN)
Source or Sink Current on VT Pin
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance
(Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
(Note 3)
QFN−16
QFN−16
QFN−16
Continuous
Surge
"2.0
50
100
−40
to +85
−65
to +150
42
35
4
265
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Condition 1
GND = 0 V
GND = 0 V
−0.5
V
v
V
Io
v
V
CC
+ 0.5 V
Condition 2
Rating
4.0
4.0
"50
Unit
V
V
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6L14
Table 5. DC CHARACTERISTICS, Multi−Level Inputs, LVPECL Outputs
V
CC
= 2.375 V to 3.63 V, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
I
CC
V
OH
Characteristic
Power Supply Current (Inputs and Outputs Open)
Min
35
Typ
47
Max
65
Unit
mA
LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS
Output HIGH Voltage (Notes 4 and 5) (Q, Q)
V
CC
= 3.3 V
V
CC
= 2.5 V
V
OL
Output LOW Voltage (Notes 4 and 5) (Q, Q)
V
CC
= 3.3 V
V
CC
= 2.5 V
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(See Figures 10 and 11)
V
th
V
IH
V
IL
V
ISE
V
REFAC
V
REFAC
V
IHD
V
ILD
V
CMR
V
ID
I
IH
I
IL
Output Reference Voltage (V
CC
w
2.5 V)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
(Note 8)
Differential Input Voltage (IN−IN) (V
IHD−
V
ILD
)
Input HIGH Current
(VT Open)
Input LOW Current
(VT Open)
IN/IN
IN/IN
V
CC
−
1.525
1200
GND
950
100
−150
−150
V
CC
−
1.425
V
CC
−
1.325
V
CC
V
IHD
−
100
V
CC
– 50
V
CC
−
GND
+150
+150
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(See Figures 12 and 13) (Note 7)
mV
mV
mV
mV
mA
mA
Input Threshold Reference Voltage Range (Note 6)
Single−Ended Input High Voltage
Single−Ended Input LOW Voltage
Single−Ended Input Voltage Amplitude (V
IH
−
V
IL
)
1100
V
th
+ 100
GND
200
V
CC
−
100
V
CC
V
th
−
100
V
CC
−
GND
mV
mV
mV
mV
V
CC
−
1145
2155
1355
V
CC
−
1945
1355
555
V
CC
−
1020
2280
1480
V
CC
−
1875
1475
675
V
CC
−
895
2405
1605
V
CC
−
1695
1605
805
mV
mV
LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS
V
IH
V
IL
I
IH
I
IL
R
TIN
R
DIFF_IN
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current, V
CC
= V
IN
= 3.63 V
Input LOW Current, V
CC
= 3.63 V, V
IN
= 0 V
Internal Input Termination Resistor (IN to VT)
Differential Input Resistance (IN to IN)
2.0
GND
−10
−150
V
CC
0.8
50
0
V
V
mA
mA
TERMINATION RESISTORS
40
80
50
100
60
120
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs loaded with 50
W
to V
CC
−
2.0 V for proper operation.
5. Input and output parameters vary 1:1 with V
CC
.
6. V
th
is applied to the complementary input when operating in single−ended mode.
7. V
IHD
, V
ILD
, V
ID
and V
CMR
parameters must be complied with simultaneously.
8. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
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NB6L14
Table 6. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.63 V, GND = 0 V, T
A
=
−40°C
to +85°C (Note 9)
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPPmin
) (Note 10)
f
IN
≤
1.25 GHz
1.25 GHz
≤
f
in
≤
2.0 GHz
2.0 GHz
≤
f
in
≤
3.0 GHz
Maximum Operating Data Rate
Propagation Delay
Set−Up Time (Note 11)
Hold Time (Note 11)
Within−Device Skew (Note 12)
Device to Device Skew (Note 13)
t
JITTER
RMS Random Jitter (Note 14)
Peak−to−Peak Data Dependent Jitter
(Note 15)
V
INPP
t
r
,t
f
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
Output Rise/Fall Times @ Full Output Swing
(20%−80%)
f
IN
= 2.5 GHz
f
DATA
= 2.5 Gb/s
100
70
150
14
V
CC
−
GND
200
mV
ps
IN to Q
EN to IN, IN
EN to IN, IN
250
300
300
5.0
20
150
1.0
ps
Min
550
380
250
Typ
700
500
320
2.5
370
500
Max
Unit
mV
f
DATA
t
PD
t
S
t
H
t
SKEW
Gb/s
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing V
INPP
(min) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
– 2.0 V. Input edge rates
40 ps (20%−80%).
10. Input and output voltage swing is a single−ended measurement operating in differential mode.
11. Set−up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set−up and hold times do not apply.
12. Within device skew is measured between two different outputs under identical power supply, temperature and input conditions.
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2
^23
−1
and K28.5 at 2.5Gb/s.
V
OUTPP
OUTPUT VOLTAGE AMPLITUDE (mV)
(TYPICAL)
800
700
600
500
400
300
200
100
0
0
1
2
3
f
out
, CLOCK OUTPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus Output
Frequency at Ambient Temperature (Typical)
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