74LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs
February 1994
Revised October 2003
74LVXC4245
8-Bit Dual Supply Configurable Voltage Interface
Transceiver with 3-STATE Outputs
General Description
The LVXC4245 is a 24-pin dual-supply, 8-bit configurable
voltage interface transceiver suited for PCMCIA and other
real time configurable I/O applications. The V
CCA
pin
accepts a 5V supply level. The “A” Port is a dedicated 5V
port. The V
CCB
pin accepts a 3V-to-5V supply level. The
“B” Port is configured to track the V
CCB
supply level
respectively. A 5V level on the V
CC
pin will configure the
I/O pins at a 5V level and a 3V V
CC
will configure the I/O
pins at a 3V level. This device will allow the V
CCB
voltage
source pin and I/O pins on the “B” Port to float when OE is
HIGH. This feature is necessary to buffer data to and from
a PCMCIA socket that permits PCMCIA cards to be
inserted and removed during normal operation.
Features
s
Bidirectional interface between 5V and 3V-to-5V buses
s
Control inputs compatible with TTL level
s
Outputs source/sink up to 24 mA
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Implements patented EMI reduction circuitry
s
Flexible V
CCB
operating range
s
Allows B Port and V
CCB
to float simultaneously when OE
is HIGH
s
Functionally compatible with the 74 series 245
Ordering Code:
Order Number
74LVXC4245WM
74LVXC4245QSC
74LVXC4245MTC
Package Number
M24B
MQA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
T/R
A
0
–A
7
B
0
–B
7
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 2003 Fairchild Semiconductor Corporation
DS012009
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74LVXC4245
Truth Table
Inputs
OE
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Outputs
T/R
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
Logic Diagram
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2
74LVXC4245
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CCA
,V
CCB
)
DC Input Voltage (V
I
) @ OE, T/R
DC Input/Output Voltage (V
I/O
)
@ A
n
@ B
n
DC Input Diode Current (I
IK
)
@ OE, T/R
DC Output Diode Current (I
OK
)
DC Output Source or
Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
and Max Current
Storage Temperature Range (T
STG
)
DC Latch-Up Source or
Sink Current
−
0.5V to
+
7.0V
−
0.5V to V
CCA
+
0.5V
−
0.5V to V
CCA
+
0.5V
−
0.5V to V
CCB
+
0.5V
±
20 mA
±
50 mA
±
50 mA
±
50 mA
±
200 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage
V
CCB
Input Voltage (V
I
) @ OE, T/R
Input/Output Voltage (V
I/O
)
@A
n
@B
n
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
V/
∆
t)
V
IN
from 30% to 70% of V
CC
V
CC
@ 3V, 4.5V, 5.5V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
The A Port unused pins (inputs and I/O's) must be held HIGH or
LOW. They may not float.
V
CCA
4.5V to 5.5V
2.7V to 5.5V
0V to V
CCA
0V to V
CCA
0V to V
CCB
−
40
°
C to
+
85
°
C
8 ns/V
DC Electrical Characteristics
Symbol
V
IHA
Parameter
Minimum HIGH Level
Input Voltage
V
IHB
A
n
OE
T/R
B
n
V
CCA
(V)
4.5
4.5
5.5
4.5
4.5
4.5
V
ILA
Maximum LOW Level
Input Voltage
V
ILB
A
n
OE
T/R
B
n
4.5
4.5
5.5
4.5
4.5
4.5
V
OHA
V
OHB
Minimum HIGH Level
Output Voltage
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
V
OLA
V
OLB
Maximum LOW Level
Output Voltage
4.5
4.5
4.5
4.5
4.5
4.5
4.5
I
IN
Maximum Input
Leakage Current @
OE, T/R
5.5
5.5
3.6
5.5
±0.1
±0.1
±1.0
±1.0
µA
V
CCB
(V)
2.7
3.6
5.5
2.7
3.6
5.5
2.7
3.6
5.5
2.7
3.6
5.5
3.0
3.0
3.0
3.0
3.0
2.7
2.7
4.5
3.0
3.0
3.0
3.0
2.7
2.7
4.5
4.49
4.25
2.99
2.85
2.65
2.5
2.3
4.25
0.002
0.21
0.002
0.21
0.11
0.22
0.18
T
A
= +25°C
Typ
2.0
2.0
2.0
2.0
2.0
3.85
0.8
0.8
0.8
0.8
0.8
1.65
4.4
3.86
2.9
2.56
2.35
2.3
2.1
3.86
0.1
0.36
0.1
0.36
0.36
0.42
0.36
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
2.0
2.0
2.0
3.85
0.8
0.8
0.8
0.8
0.8
1.65
4.4
3.76
2.9
2.46
2.25
2.2
2.0
3.76
0.1
0.44
0.1
0.44
0.44
0.5
0.44
V
V
V
V
I
OUT
= −100 µA
I
OH
= −24
mA
I
OUT
= −100 µA
I
OH
= −12
mA
I
OH
= −24
mA
I
OH
= −12
mA
I
OH
= −24
mA
I
OH
= −24
mA
I
OUT
=
100
µA
I
OL
=
24 mA
I
OUT
=
100
µA
I
OL
=
24 mA
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
24 mA
V
I
=
V
CCA
, GND
V
V
OUT
≤
0.1V
or
≥
V
CC
−
0.1V
V
Units
Conditions
V
OUT
≤
0.1V
or
≥
V
CC
−
0.1V
3
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74LVXC4245
DC Electrical Characteristics
Symbol
I
OZA
Parameter
Maximum 3-STATE
Output Leakage @ A
n
I
OZB
∆I
CC
I
CCA1
Maximum 3-STATE
Output Leakage @ B
n
Maximum
I
CC
/Input
Quiescent V
CCA
Supply Current as B
Port Floats
I
CCA2
Quiescent V
CCA
Supply Current
I
CCB
Quiescent V
CCB
Supply Current
V
OLPA
V
OLPB
V
OLVA
V
OLVB
V
IHDA
V
IHDB
V
ILDA
V
ILDB
Minimum HIGH Level
Dynamic Input
Voltage
Maximum LOW Level
Dynamic Input
Voltage
Quiet Output
Maximum Dynamic
V
OL
Quiet Output Minimum
Dynamic V
OL
5.5
5.5
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Note 3:
Worst case package.
(Continued)
V
CCB
(V)
3.6
5.5
3.6
5.5
5.5
3.6
Open
1.0
T
A
= +25°C
Typ
±0.5
±0.5
±0.5
±0.5
1.35
0.35
8
T
A
= −40°C
to
+85°C
Guaranteed Limits
±5.0
±5.0
±5.0
±5.0
1.5
0.5
80
µA
µA
mA
mA
µA
V
I
=
V
IL
, V
IH
, OE
=
V
CCA
V
O
=
V
CCA
, GND
V
I
=
V
IL
, V
IH
, OE
=
V
CCA
V
O
=
V
CCB
, GND
V
I
=
V
CC
−
2.1V
V
I
=
V
CCB
−
0.6V
A
n
=
V
CCA
or GND
B
n
=
Open, OE
=
V
CCA
T/R
=
V
CCA
, V
CCB
=
Open
A
n
=
V
CCA
or GND
V
CCA
(V)
5.5
5.5
5.5
5.5
All Inputs
B
n
5.5
5.5
5.5
Units
Conditions
5.5
5.5
3.6
5.5
3.6
5.5
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
8
8
5
8
1.5
1.5
0.8
1.5
−1.2
−1.2
−0.8
−1.2
2.0
2.0
2.0
3.5
0.8
0.8
0.8
1.5
80
80
50
80
µA
B
n
=
V
CCB
or GND
OE
=
GND, T/R
=
GND
A
n
=
V
CCA
or GND
µA
B
n
=
V
CCB
or GND
OE
=
GND, T/R
=
V
CCA
(Note 3) (Note 4)
(Note 3) (Note 4)
(Note 3) (Note 4)
(Note 3) (Note 4)
(Note 3) (Note 5)
(Note 3) (Note 5)
(Note 3) (Note 5)
(Note 3) (Note 5)
V
V
V
V
V
V
V
V
Note 4:
Max number of outputs defined as (n). Data inputs are driven 0V to V
CC
level; one output at GND.
Note 5:
Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to V
CC
level. Input-under-test switching:
V
CC
level to threshold (V
IHD
), 0V to threshold (V
ILD
), f
=
1 MHz.
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4
74LVXC4245
AC Electrical Characteristics
C
L
=
50 pF
V
CCA
=
4.5V to 5.5V
Symbol
Parameter
Min
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PZL
t
PZH
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Propagation
Delay A to B
Propagation
Delay B to A
Output Enable
Time OE to B
Output Enable
Time OE to A
Output Disable
Time OE to B
Output Disable
Time OE to A
Output to Output
Skew (Note 8)
Data to Output
Note 6:
Typical values at V
CCA
=
5V, V
CCB
=
5V @25°C.
Note 7:
Typical values at V
CCA
=
5V, V
CCB
=
3.3V @25°C.
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
C
L
=
50 pF
V
CCA
=
4.5V to 5.5V
V
CCB
=
2.7V to 3.6V
T
A
= +25°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
(Note 7)
5.5
5.0
5.6
4.3
6.7
6.9
8.0
6.3
6.0
4.2
3.4
2.9
1.0
Max
7.5
7.0
7.5
6.0
9.0
9.5
10.0
8.0
9.0
6.5
5.5
5.0
1.5
T
A
= −40°C
to
+85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
8.0
7.5
8.0
6.5
10.0
10.0
11.0
8.5
9.5
7.0
6.0
5.5
1.5
Units
V
CCB
=
4.5V to 5.5V
T
A
= +25°C
Typ
(Note 6)
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
4.9
4.0
4.7
3.9
5.6
5.7
7.4
6.1
4.8
3.8
3.4
2.9
1.0
6.5
5.5
6.5
5.0
7.5
7.5
9.0
7.5
7.0
5.5
5.5
4.5
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
7.0
6.0
7.0
5.5
8.0
8.0
10.0
8.5
7.5
6.0
6.0
5.0
1.5
Max
T
A
= −40°C
to
+85°C
Min
Max
ns
ns
ns
ns
ns
ns
ns
Capacitance
Symbol
C
IN
C
I/O
C
PD
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
(Note 9)
Note 9:
C
PD
is measured at 10 MHz.
Parameter
Typ
4.5
10
A→B
B→A
45
50
Units
pF
pF
pF
pF
V
CC
=
Open
Conditions
V
CCA
=
5V, V
CCB
=
3.3V
V
CCA
=
5V
V
CCB
=
3.3V
Power Up Considerations
To insure the system does not experience unnecessary I
CC
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
• Power up the control side of the device first. This is the
V
CCA
.
• OE should ramp with or ahead of V
CCA
. This will help
guard against bus contention.
• The Transmit/Receive control pin (T/R) should ramp with
V
CCA
, this will ensure that the A Port data pins are con-
figured as inputs. With V
CCA
receiving power first, the A
I/O Port should be configured as inputs to help guard
against bus contention and oscillations.
• A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Device Type
74LVXC4245
V
CCA
5V
(power up 1st)
V
CCB
2.7V to 5.5V
configurable
T/R
ramp
with V
CCA
OE
ramp
with V
CCA
A Side I/O
logic
0V or V
CCA
B Side I/O
outputs
Floatable Pin
Allowed
yes, V
CCB
and B
I/O’s w/ OE HIGH
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
5
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