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74LVX573MX_NL

产品描述Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20
产品类别逻辑    逻辑   
文件大小91KB,共7页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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74LVX573MX_NL概述

Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20

74LVX573MX_NL规格参数

参数名称属性值
厂商名称Fairchild
零件包装代码SOIC
包装说明SOP,
针数20
Reach Compliance Codeunknown
其他特性BROADSIDE VERSION OF 373
系列LV/LV-A/LVX/H
JESD-30 代码R-PDSO-G20
JESD-609代码e3
长度12.8 mm
逻辑集成电路类型BUS DRIVER
位数8
功能数量1
端口数量2
端子数量20
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE
传播延迟(tpd)22 ns
认证状态Not Qualified
座面最大高度2.65 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)2.7 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层MATTE TIN
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
宽度7.5 mm
Base Number Matches1

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74LVX573 Low Voltage Octal Latch with 3-STATE Outputs
June 1993
Revised April 2005
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVX573 is functionally identical to
the LVX373 but with inputs and outputs on opposite sides
of the package. The inputs tolerate up to 7V allowing inter-
face of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX573M
74LVX573SJ
74LVX573MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
© 2005 Fairchild Semiconductor Corporation
DS011616
www.fairchildsemi.com

 
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