74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
June 1993
Revised April 2005
74LVX373
Low Voltage Octal Transparent Latch with
3-STATE Outputs
General Description
The LVX373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The latches appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state. The inputs tolerate
up to 7V allowing interface of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX373M
74LVX373SJ
74LVX373MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Logic Symbols
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Description
IEEE/IEC
O
0
–O
7
Truth Table
Inputs
LE
X
H
OE
H
L
L
L
D
n
X
L
H
X
Outputs
O
n
Z
L
H
O
0
Connection Diagram
H
L
Z
X
O
0
H
L
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Previous O
0
before HIGH-to-LOW transition of Latch Enable
© 2005 Fairchild Semiconductor Corporation
DS011613
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74LVX373
Functional Description
The LVX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The 3-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the
standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74LVX373
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
0.5V to
7.0V
20 mA
0.5V to 7V
20 mA
20 mA
0.5V to V
CC
0.5V
r
25 mA
r
75 mA
65
q
C to
150
q
C
180 mW
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Input Rise and Fall Time (
'
t/
'
V)
2.0V to 3.6V
0V to 5.5V
0V to V
CC
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
40
q
C to
85
q
C
0 ns/V to 100 ns/V
0.5V
V
CC
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature (T
STG
)
Power Dissipation
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level
Input Voltage
V
IL
LOW Level
Input Voltage
V
OH
HIGH Level
Output Voltage
V
OL
LOW Level
Output Voltage
I
OZ
I
IN
I
CC
3-STATE Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
3.6
3.6
V
CC
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
2.0
3.0
T
A
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.44
V
V
IN
V
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Min
1.5
2.0
2.4
0.5
0.8
0.8
Max
Units
Conditions
V
V
V
IN
V
IH
or V
IL
I
OH
I
OH
I
OH
V
IH
or V
IL
I
OL
I
OL
I
OL
V
IH
or V
IL
V
CC
or GND
5.5V or GND
V
CC
or GND
50
P
A
50
P
A
4 mA
50
P
A
50
P
A
4 mA
r
0.25
r
0.1
4.0
r
2.5
r
1.0
40.0
P
A
P
A
P
A
V
IN
V
OUT
V
IN
V
IN
Noise Characteristics
(Note 3)
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
t
f
3 ns.
V
CC
(V)
3.3
3.3
3.3
3.3
T
A
Typ
0.5
25
q
C
Limit
0.8
Units
V
V
V
V
C
L
(pF)
50
50
50
50
0.5
0.8
2.0
0.8
Note 3:
Input t
r
3
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74LVX373
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay Time
D
n
to O
n
3.3
r
0.3
t
PLH
t
PHL
Propagation Delay Time
LE to O
n
3.3
r
0.3
t
PZL
t
PZH
3-STATE Output
Enable Time
3.3
r
0.3
t
PLZ
t
PHZ
t
W
t
S
t
H
t
OSLH
t
OSHL
3-STATE Output
Disable Time
LE Pulse Width, HIGH
Setup Time, D
n
to LE
Hold Time, D
n
to LE
Output to Output Skew
(Note 4)
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
|t
PLHm
t
PLHn
|, t
OSHL
V
CC
(V)
2.7
Min
T
A
25
q
C
Typ
7.7
10.2
6.0
8.5
7.5
10.0
5.8
8.3
7.7
10.2
6.0
8.5
9.8
8.2
Max
15.0
18.5
9.7
13.2
14.5
18.0
9.3
12.8
15.0
18.5
9.7
13.2
18.0
12.8
T
A
40
q
C to
85
q
C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
7.5
5.0
6.0
4.0
1.0
1.0
Max
18.5
22.0
11.5
15.0
17.5
21.0
11.0
14.5
18.5
22.0
11.5
15.0
21.0
14.5
Units
C
L
ns
C
L
C
L
C
L
C
L
ns
C
L
C
L
C
L
C
L
ns
C
L
C
L
C
L
ns
ns
ns
ns
C
L
C
L
Conditions
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF, R
L
50 pF, R
L
15 pF, R
L
50 pF, R
L
50 pF, R
L
50 pF, R
L
1 k
:
1 k
:
1 k
:
1 k
:
1 k
:
1 k
:
2.7
2.7
6.5
5.0
6.0
4.0
1.0
1.0
1.5
1.5
|t
PHLm
t
PHLn
|
1.5
1.5
ns
C
L
50 pF
Note 4:
Parameter guaranteed by design. t
OSLH
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter
T
A
Min
25
q
C
Typ
4
6
27
Max
10
T
A
40
q
C to
85
q
C
Min
Max
10
Units
pF
pF
pF
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4
74LVX373
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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