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74LVX273 Low Voltage Octal D-Type Flip-Flop
June 1993
Revised April 2005
74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX273M
74LVX273SJ
74LVX273MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Truth Table
Pin Descriptions
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Description
Reset (Clear)
Load '1'
Load '0'
H HIGH Voltage Level
L LOW Voltage Level
Operating Mode
MR
L
H
H
Inputs
CP
D
n
X
H
L
Outputs
Q
n
L
H
L
X
X
Immaterial
LOW-to-HIGH Transition
© 2005 Fairchild Semiconductor Corporation
DS011614
www.fairchildsemi.com
74LVX273
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74LVX273
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
0.5V to
7.0V
20 mA
0.5V to 7V
20 mA
20 mA
0.5V to V
CC
0.5V
r
25 mA
r
75 mA
65
q
C to
150
q
C
180 mW
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Input Rise and Fall Time (
'
t/
'
V)
2.0V to 3.6V
0V to 5.5V
0V to V
CC
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
40
q
C to
85
q
C
0 ns/V to 100 ns/V
0.5V
V
CC
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature (T
STG
)
Power Dissipation
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level
Input Voltage
V
IL
LOW Level
Input Voltage
V
OH
HIGH Level
Output Voltage
V
OL
LOW Level
Output Voltage
I
OZ
I
IN
I
CC
3-STATE Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
3.6
3.6
V
CC
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
2.0
3.0
T
A
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.44
V
V
IN
V
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Min
1.5
2.0
2.4
0.5
0.8
0.8
Max
Units
Conditions
V
V
V
IN
V
IH
or V
IL
I
OH
I
OH
I
OH
V
IH
or V
IL
I
OL
I
OL
I
OL
V
IH
or V
IL
V
CC
or GND
5.5V or GND
V
CC
or GND
50
P
A
50
P
A
4 mA
50
P
A
50
P
A
4 mA
r
0.25
r
0.1
4.0
r
2.5
r
1.0
40.0
P
A
P
A
P
A
V
IN
V
OUT
V
IN
V
IN
Noise Characteristics
(Note 3)
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
t
f
3ns
V
CC
(V)
3.3
3.3
3.3
3.3
T
A
Typ
0.5
25
q
C
Limit
0.8
Units
V
V
V
V
C
L
(pF)
50
50
50
50
0.5
0.8
2.0
0.8
Note 3:
Input t
r
3
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74LVX273
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation
Delay Time
CP to Q
n
t
PHL
Propagation Delay
MR to Q
n
3.3
r
0.3
t
S
t
H
t
REC
t
W
Setup Time
D
n
to CP
Hold Time
D
n
to CP
Removal Time
MR to CP
Clock Pulse
Width
t
W
f
MAX
MR Pulse
Width
Maximum
Clock
Frequency
t
OSLH
t
OSHL
Output to Output
Skew (Note 4)
3.3
r
0.3
2.7
3.3
|t
PLHm
t
PLHn
|, t
OSHL
V
CC
(V)
2.7
3.3
r
0.3
2.7
Min
T
A
25
q
C
Typ
9.0
11.5
7.1
9.6
9.3
11.8
7.3
9.8
Max
16.9
20.0
11.0
14.5
17.8
21.1
11.5
15.0
T
A
40
q
C to
85
q
C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
9.5
6.5
1.0
1.0
4.0
2.5
9.5
6.5
8.5
6.0
Max
20.5
24.0
13.0
16.5
20.5
24.0
13.5
17.0
Units
C
L
(pF)
15
ns
50
15
50
15
50
15
50
ns
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
3.3
r
0.3
2.7
8.0
5.5
1.0
1.0
4.0
2.5
8.0
5.5
7.5
5.0
55
45
95
60
110
60
150
90
1.5
1.5
|t
PHLm
t
PHLn
|
ns
ns
ns
ns
ns
15
MHz
50
15
50
1.5
1.5
ns
50
45
40
80
50
Note 4:
Parameter guaranteed by design. t
OSLH
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter
T
A
Min
25
q
C
Typ
4
6
31
Max
10
T
A
40
q
C to
85
q
C
Min
Max
10
Units
pF
pF
pF
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