Datasheet> 器件分类 > 模拟混合信号IC> 驱动程序和接口> 74LVX161284MTD_NL

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74LVX161284MTD_NL: 产品描述Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, LEAD FREE, MO-153, TSSOP-48; 产品类别模拟混合信号IC 驱动程序和接口; 文件大小112KB，共11页; 制造商Fairchild; 官网地址http://www.fairchildsemi.com/

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74LVX161284MTD_NL概述

Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, LEAD FREE, MO-153, TSSOP-48

74LVX161284MTD_NL规格参数

参数名称	属性值
厂商名称	Fairchild
零件包装代码	TSSOP
包装说明	TSSOP,
针数	48
Reach Compliance Code	unknown
ECCN代码	EAR99
其他特性	CONTAINS EIGHT BIDIRECTIONAL DATA BUFFERS
差分输出	NO
驱动器位数	14
输入特性	SCHMITT TRIGGER
接口集成电路类型	LINE TRANSCEIVER
接口标准	IEEE 1284
JESD-30 代码	R-PDSO-G48
JESD-609代码	e3/e4
长度	12.5 mm
功能数量	13
端子数量	48
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	TSSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态	Not Qualified
最大接收延迟	44 ns
接收器位数	13
座面最大高度	1.2 mm
最大供电电压	3.6 V
最小供电电压	3 V
标称供电电压	3.3 V
电源电压1-最大	5.5 V
电源电压1-分钟	3 V
电源电压1-Nom	3.15 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	MATTE TIN/NICKEL PALLADIUM GOLD
端子形式	GULL WING
端子节距	0.5 mm
端子位置	DUAL
最大传输延迟	44 ns
宽度	6.1 mm
Base Number Matches	1

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74LVX161284 Low Voltage IEEE 161284 Translating Transceiver

January 1999

Revised June 2005

74LVX161284

Low Voltage IEEE 161284 Translating Transceiver

General Description

The LVX161284 contains eight bidirectional data buffers

and eleven control/status buffers to implement a full

IEEE 1284 compliant interface. The device supports the

IEEE 1284 standard and is intended to be used in an

Extended Capabilities Port mode (ECP). The pinout allows

for easy connection from the Peripheral (A-side) to the

Host (cable side).

Outputs on the cable side can be configured to be either

open drain or high drive (

14 mA) and are connected to a

separate power supply pin (V

-cable) to allow these out-

puts to be driven by a higher supply voltage than the A-

side. The pull-up and pull-down series termination resis-

tance of these outputs on the cable side is optimized to

drive an external cable. In addition, all inputs (except HLH)

and outputs on the cable side contain internal pull-up resis-

tors connected to the V

-cable supply to provide proper

termination and pull-ups for open drain mode.

Outputs on the Peripheral side are standard low-drive

CMOS outputs designed to interface with 3V logic. The DIR

input controls data flow on the A

–A

–B

transceiver

pins.

Features

Supports IEEE 1284 Level 1 and Level 2 signaling

standards for bidirectional parallel communications

between personal computers and printing peripherals

Translation capability allows outputs on the cable side to

interface with 5V signals

All inputs have hysteresis to provide noise margin

B and Y output resistance optimized to drive external

cable

B and Y outputs in high impedance mode during power

down

Inputs and outputs on cable side have internal pull-up

resistors

Flow-through pin configuration allows easy interface

between the “Peripheral and Host”

Replaces the function of two (2) 74ACT1284 devices

Ordering Code

Order Number

74LVX161284MEA

74LVX161284MTD

Package Number

MS48A

MTD48

Package Description

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

DIR

–A

–B

–A

–Y

–A

–C

PLH

HLH

Description

High Drive Enable Input (Active HIGH)

Direction Control Input

Inputs or Outputs

Inputs

Outputs

Inputs

Peripheral Logic HIGH Input

Peripheral Logic HIGH Output

Host Logic HIGH Input

Host Logic HIGH Output

DS500202

www.fairchildsemi.com

74LVX161284MTD_NL相似产品对比

	74LVX161284MTD_NL	74LVX161284MEA_NL
描述	Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, LEAD FREE, MO-153, TSSOP-48	Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
厂商名称	Fairchild	Fairchild
零件包装代码	TSSOP	SSOP
包装说明	TSSOP,	SSOP,
针数	48	48
Reach Compliance Code	unknown	unknown
ECCN代码	EAR99	EAR99
差分输出	NO	NO
驱动器位数	14	14
输入特性	SCHMITT TRIGGER	SCHMITT TRIGGER
接口集成电路类型	LINE TRANSCEIVER	LINE TRANSCEIVER
接口标准	IEEE 1284	IEEE 1284
JESD-30 代码	R-PDSO-G48	R-PDSO-G48
JESD-609代码	e3/e4	e3
长度	12.5 mm	15.875 mm
功能数量	13	13
端子数量	48	48
最高工作温度	85 °C	85 °C
最低工作温度	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	SSOP
封装形状	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
认证状态	Not Qualified	Not Qualified
最大接收延迟	44 ns	44 ns
接收器位数	13	13
座面最大高度	1.2 mm	2.74 mm
最大供电电压	3.6 V	3.6 V
最小供电电压	3 V	3 V
标称供电电压	3.3 V	3.3 V
电源电压1-最大	5.5 V	5.5 V
电源电压1-分钟	3 V	3 V
电源电压1-Nom	3.15 V	3.3 V
表面贴装	YES	YES
技术	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL
端子面层	MATTE TIN/NICKEL PALLADIUM GOLD	MATTE TIN
端子形式	GULL WING	GULL WING
端子节距	0.5 mm	0.635 mm
端子位置	DUAL	DUAL
最大传输延迟	44 ns	44 ns
宽度	6.1 mm	7.495 mm
Base Number Matches	1	1

74LVX161284MTD_NL

74LVX161284MTD_NL概述

74LVX161284MTD_NL规格参数

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