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7054S35PRF

产品描述TQFP-128, Tray
产品类别存储    存储   
文件大小417KB,共12页
制造商IDT (Integrated Device Technology)
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7054S35PRF概述

TQFP-128, Tray

7054S35PRF规格参数

参数名称属性值
Brand NameIntegrated Device Technology
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码TQFP
包装说明QFF, QFP128,.67X.93,20
针数128
制造商包装代码PK128
Reach Compliance Codenot_compliant
ECCN代码EAR99
最长访问时间35 ns
其他特性AUTOMATIC POWER DOWN; LOW POWER STANDBY MODE
I/O 类型COMMON
JESD-30 代码R-PQFP-F128
JESD-609代码e0
长度20 mm
内存密度32768 bit
内存集成电路类型FOUR-PORT SRAM
内存宽度8
湿度敏感等级3
功能数量1
端口数量4
端子数量128
字数4096 words
字数代码4000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织4KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码QFF
封装等效代码QFP128,.67X.93,20
封装形状RECTANGULAR
封装形式FLATPACK
并行/串行PARALLEL
峰值回流温度(摄氏度)225
电源5 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.0015 A
最小待机电流4.5 V
最大压摆率0.335 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式FLAT
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度14 mm
Base Number Matches1

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HIGH-SPEED
4K x 8 FourPort
TM
STATIC RAM
Features
Description
7054L
High-speed access
– Commercial: 20ns (max.)
Low-power operation
– IDT7054L
Active: 750mW (typ.)
Standby: 1.5mW (typ.)
True FourPort memory cells which allow simultaneous
access of the same memory locations
Fully asynchronous operation from each of the four ports:
P1, P2, P3, and P4
TTL-compatible; single 5V (±10%) power supply
Available in 128 pin Thin Quad Flatpack package
Green parts available, see ordering information
The IDT7054 is a high-speed 4K x 8 FourPort™ Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This FourPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT7054 is also designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be able to
externally arbitrated or withstand contention when all ports simulta-
neously access the same FourPort RAM location.
The IDT7054 provides four independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
Functional Block Diagram
R/
W
P1
CE
P1
OE
P1
CE
P4
R/
W
P4
OE
P4
I/O
0P1
-I/O
7P1
COLUMN
I/O
COLUMN
I/O
I/O
0P4
-I/O
7P4
A
0P1
- A
11P1
PORT 1
ADDRESS
DECODE
LOGIC
PORT 2
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
PORT 4
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
A
0P4
- A
11P4
A
0P2
- A
11P2
A
0P3
- A
11P3
I/O
0P2
-I/O
7P2
OE
P2
CE
P2
R/
W
P2
COLUMN
I/O
COLUMN
I/O
I/O
0P3
-I/O
7P3
OE
P3
CE
P3
R/
W
P3
3241 drw 01
JULY 2019
1
DSC 3241/15

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