NSS35200CF8T1G
35 V, 7 A, Low V
CE(sat)
PNP Transistor
ON Semiconductor’s e
2
PowerEdge family of low V
CE(sat)
transistors are miniature surface mount devices featuring ultra low
saturation voltage (V
CE(sat)
) and high current gain capability. These
are designed for use in low voltage, high speed switching applications
where affordable efficient energy control is important.
Typical application are DC−DC converters and power management
in portable and battery powered products such as cellular and cordless
phones, PDAs, computers, printers, digital cameras and MP3 players.
Other applications are low voltage motor controls in mass storage
products such as disc drives and tape drives. In the automotive
industry they can be used in air bag deployment and in the instrument
cluster. The high current gain allows e
2
PowerEdge devices to be
driven directly from PMU’s control outputs, and the Linear Gain
(Beta) makes them ideal components in analog amplifiers.
Features
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35 VOLTS
7.0 AMPS
PNP LOW V
CE(sat)
TRANSISTOR
EQUIVALENT R
DS(on)
78 mW
COLLECTOR
1, 2, 3, 6, 7, 8
•
This is a Pb−Free Device
MAXIMUM RATINGS
(T
A
= 25°C)
Rating
Collector-Emitter Voltage
Collector-Base Voltage
Emitter-Base Voltage
Collector Current − Continuous
Collector Current − Peak
Electrostatic Discharge
Symbol
V
CEO
V
CBO
V
EBO
I
C
I
CM
ESD
Max
−35
−55
−5.0
−2.0
−7.0
Unit
Vdc
Vdc
Vdc
Adc
A
4
BASE
5
EMITTER
ChipFET]
CASE 1206A
STYLE 4
HBM Class 3
MM Class C
PIN
CONNECTIONS
C 8
1 C
2 C
3 C
4 B
1
2
3
4
MARKING
DIAGRAM
8
7
6
5
G4
M
G
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient
Thermal Resistance, Junction−to−Lead #1
Total Device Dissipation
(Single Pulse < 10 sec)
Junction and Storage
Temperature Range
Symbol
P
D
(Note 1)
R
qJA
(Note 1)
P
D
(Note 2)
R
qJA
(Note 2)
R
qJL
P
Dsingle
(Notes 2 & 3)
T
J
, T
stg
Max
635
5.1
200
1.35
11
90
15
2.75
−55 to
+150
Unit
mW
mW/°C
°C/W
W
mW/°C
°C/W
°C/W
W
°C
C 7
C 6
E 5
G4 = Specific Device Code
M = Month Code
G
= Pb−Free Package
ORDERING INFORMATION
Device
NSS35200CF8T1G
Package
ChipFET
(Pb−Free)
Shipping
†
3000/
Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ 100 mm
2
, 1 oz copper traces.
2. FR−4 @ 500 mm
2
, 1 oz copper traces.
3. Thermal response.
©
Semiconductor Components Industries, LLC, 2006
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
March, 2006 − Rev. 5
Publication Order Number:
NSS35200CF8T1G/D
NSS35200CF8T1G
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Collector −Emitter Breakdown Voltage
(I
C
= −10 mAdc, I
B
= 0)
Collector −Base Breakdown Voltage
(I
C
= −0.1 mAdc, I
E
= 0)
Emitter −Base Breakdown Voltage
(I
E
= −0.1 mAdc, I
C
= 0)
Collector Cutoff Current
(V
CB
= −35 Vdc, I
E
= 0)
Collector−Emitter Cutoff Current
(V
CES
= −35 Vdc)
Emitter Cutoff Current
(V
EB
= −6.0 Vdc)
ON CHARACTERISTICS
DC Current Gain (Note 4)
(I
C
= −1.0 A, V
CE
= −2.0 V)
(I
C
= −1.5 A, V
CE
= −2.0 V)
(I
C
= −2.0 A, V
CE
= −2.0 V)
Collector −Emitter Saturation Voltage (Note 4)
(I
C
= −0.1 A, I
B
= −0.010 A)
(I
C
= −1.0 A, I
B
= −0.010 A)
(I
C
= −2.0 A, I
B
= −0.02 A)
Base −Emitter Saturation Voltage (Note 4)
(I
C
= −1.0 A, I
B
= −0.01 A)
Base −Emitter Turn−on Voltage (Note 4)
(I
C
= −2.0 A, V
CE
= −3.0 V)
Cutoff Frequency
(I
C
= −100 mA, V
CE
= −5.0 V, f = 100 MHz)
Input Capacitance (V
EB
= −0.5 V, f = 1.0 MHz)
Output Capacitance (V
CB
= −3.0 V, f = 1.0 MHz)
Turn−on Time (V
CC
= −10 V, I
B1
= −100 mA, I
C
= −1 A, R
L
= 3
W)
Turn−off Time (V
CC
= −10 V, I
B1
= I
B2
= −100 mA, I
C
= 1 A, R
L
= 3
W)
4. Pulsed Condition: Pulse Width = 300
msec,
Duty Cycle
≤
2%
h
FE
100
100
100
V
CE(sat)
−
−
−
V
BE(sat)
−
V
BE(on)
−
f
T
100
Cibo
Cobo
t
on
t
off
−
−
−
−
−
600
85
35
225
−
650
100
−
−
pF
pF
nS
nS
−0.81
−0.875
MHz
−0.68
−0.85
V
−
−
−
−0.10
−0.15
−0.30
V
200
200
200
−
400
−
V
V
(BR)CEO
−35
V
(BR)CBO
−55
V
(BR)EBO
−5.0
I
CBO
−
I
CES
−
I
EBO
−
−0.01
−0.1
−0.03
−0.1
mAdc
−0.03
−0.1
mAdc
−7.0
−
mAdc
−65
−
Vdc
−45
−
Vdc
Vdc
Symbol
Min
Typical
Max
Unit
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2
NSS35200CF8T1G
VCE(sat), COLLECTOR EMITTER SATURATION
VOLTAGE (VOLTS)
VCE(sat), COLLECTOR EMITTER SATURATION
VOLTAGE (VOLTS)
0.25
I
C
/I
B
= 50
0.20
100°C
0.15
25°C
0.10
0.05
0
−55°C
0.1
I
C
/I
B
= 100
50
10
0.01
0.001
0.001
0.01
0.1
1.0
0.001
0.01
0.1
1.0
I
C
, COLLECTOR CURRENT (A)
I
C
, COLLECTOR CURRENT (A)
Figure 1. Collector Emitter Saturation Voltage
versus Collector Current
Figure 2. Collector Emitter Saturation Voltage
versus Collector Current
500
450
400
hFE , DC CURRENT GAIN
350
300
250
200
VBE(sat) , BASE EMITTER SATURATION
VOLTAGE (VOLTS)
125°C (5 V)
125°C (2 V)
25°C (5 V)
25°C (2 V)
−55°C (5 V)
−55°C (2 V)
1.0
0.8
0.6
0.4
0.2
0
−55°C
25°C
100°C
150
100
50
0
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1.0
I
C
, COLLECTOR CURRENT (A)
I
C
, COLLECTOR CURRENT (A)
Figure 3. DC Current Gain versus
Collector Current
V BE(on) , BASE EMITTER TURN−ON VOLTAGE (VOLTS)
1.1
C ibo , INPUT CAPACITANCE (pF)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.001
0.01
0.1
1.0
100°C
25°C
−55°C
750
700
650
600
550
500
450
400
350
300
0
Figure 4. Base Emitter Saturation Voltage
versus Collector Current
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
I
C
, COLLECTOR CURRENT (A)
V
EB
, EMITTER BASE VOLTAGE (V)
Figure 5. Base Emitter Turn−On Voltage
versus Collector Current
Figure 6. Input Capacitance
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3
NSS35200CF8T1G
225
Cobo, OUTPUT CAPACITANCE (pF)
200
175
150
I
C
, (A)
125
100
75
50
25
0
0.01
0
5.0
10
15
20
25
30
35
0.10
1
V
CE
, (Vdc)
10
100
1.00
Thermal Limits
0.10
10
1s
1 ms
10 ms
100 ms
V
CB
, COLLECTOR BASE VOLTAGE (V)
Figure 7. Output Capacitance
Figure 8. Safe Operating Area
R
(t)
, TRANSIENT THERMAL RESISTANCE
1000
D = 0.10
100
D = 0.20
10
D = 0.05
1
D = 0.01
t
1
0.1
Single Pulse
t
2
Duty Cycle = D = t
1
/t
2
q
JC
= 174°C/W
t
1
, TIME (Sec)
D = 0.50
P(pk)
0.01
Figure 9. Normalized Thermal Response
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4
NSS35200CF8T1G
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE PRELIMINARY
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED
0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET
IN HORIZONTAL AND VERTICAL SHALL
NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF
MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP
AND BOTTOM LEAD SURFACE.
MILLIMETERS
MIN
MAX
2.95
3.10
1.55
1.70
1.00
1.10
0.25
0.35
0.65 BSC
0.10
0.20
0.28
0.42
0.55 BSC
5
°
NOM
1.80
2.00
INCHES
MIN
MAX
0.116 0.122
0.061 0.067
0.039 0.043
0.010 0.014
0.025 BSC
0.004 0.008
0.011 0.017
0.022 BSC
5
°
NOM
0.072 0.080
A
8
7
6
5
M
K
5
6
3
7
2
8
1
S
1
2
3
4
B
4
L
G
D
J
C
0.05 (0.002)
STYLE 4:
PIN 1. COLLECTOR
2. COLLECTOR
3. COLLECTOR
4. BASE
5. EMITTER
6. COLLECTOR
7. COLLECTOR
8. COLLECTOR
DIM
A
B
C
D
G
J
K
L
M
S
SOLDERING FOOTPRINT*
2.032
0.08
0.457
0.018
0.635
0.025
1.727
0.068
2.032
0.08
0.457
0.018
0.711
0.028
0.66
0.026
SCALE 20:1
mm
inches
0.178
0.007
0.711
0.028
0.66
0.026
SCALE 20:1
mm
inches
Basic
Style 4
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
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