D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
74LVX08 — Low Voltage Quad 2-Input AND Gate
February 2008
74LVX08
Low Voltage Quad 2-Input AND Gate
Features
■
Input voltage level translation from 5V to 3V
■
Ideal for low power/low noise 3.3V applications
■
Guaranteed simultaneous switching noise level and
General Description
The LVX08 contains four 2-input AND gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V
systems to 3V systems.
dynamic threshold performance
Ordering Information
Order
Number
74LVX08M
74LVX08SJ
74LVX08MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
©1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.4.0
www.fairchildsemi.com
74LVX08 — Low Voltage Quad 2-Input AND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
V
I
I
OK
Supply Voltage
Parameter
DC Input Diode Current, V
I
=
–0.5V
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
Rating
–0.5V to +7.0V
–20mA
–0.5V to 7V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±25mA
±50mA
–65°C to +150°C
180mW
240°C
V
O
I
O
DC Output Voltage
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current
T
STG
Storage Temperature
P
T
L
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
Parameter
Rating
2.0V to 3.6V
0V to 5.5V
0V to V
CC
–40°C to +85°C
0ns/V to 100ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.4.0
www.fairchildsemi.com
2
74LVX08 — Low Voltage Quad 2-Input AND Gate
DC Electrical Characteristics
T
A
=
+25°C
Symbol
V
IH
T
A
=
–40°C to
+85°C
Min.
1.5
2.0
2.4
Parameter
HIGH Level Input
Voltage
V
CC
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
Conditions
Min.
1.5
2.0
2.4
Typ. Max.
Max.
Units
V
V
IL
LOW Level Input
Voltage
0.5
0.8
0.8
V
IN
=
V
IL
or V
IH
,
I
OH
=
–50µA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–50µA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–4mA
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
±0.1
2.0
2.0
3.0
1.9
2.9
2.48
0.5
0.8
0.8
V
V
OH
HIGH Level Output
Voltage
V
V
OL
LOW Level Output
Voltage
2.0
3.0
V
IN
=
V
IL
or V
IH
,
I
OL
=
50µA
V
IN
=
V
IL
or V
IH
,
I
OL
=
50µA
V
IN
=
V
IL
or V
IH
,
I
OL
=
4mA
0.1
0.1
0.44
±1.0
20.0
V
I
IN
I
CC
Input Leakage
Current
Quiescent Supply
Current
3.6
3.6
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
µA
µA
Noise Characteristics
(2)
T
A
=
25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
3.3
3.3
3.3
3.3
C
L
(pF)
50
50
50
50
Typ.
0.3
–0.3
Limit
0.5
–0.5
2.0
0.8
Units
V
V
V
V
Note:
2. Input t
r
=
t
f
=
3ns
©1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.4.0
www.fairchildsemi.com
3
74LVX08 — Low Voltage Quad 2-Input AND Gate
AC Electrical Characteristics
T
A
=
+25°C
Symbol
t
PLH
, t
PHL
T
A
=
–40°C to
+85°C
Min.
1.0
1.0
1.0
1.0
Parameter
Propagation Delay Time
V
CC
(V)
2.7
3.3 ± 0.3
C
L
(pF)
15
50
15
50
50
Min.
Typ.
6.3
8.8
4.8
7.3
Max.
11.4
14.9
7.1
10.6
1.5
1.5
Max.
13.5
17.0
8.5
12.0
1.5
1.5
Units
ns
t
OSLH
, t
OSHL
Output to Output Skew
(3)
2.7
3.3
ns
Note:
3. Parameter guaranteed by design t
OSLH
=
|t
PLHm
–t
PLHn
|, t
OSHL
=
|t
PHLm
–t
PHLn
|
Capacitance
T
A
=
+25°C
Symbol
C
IN
C
PD
T
A
=
–40°C to
+85°C
Max.
10
Parameter
Input Capacitance
Power Dissipation Capacitance
(4)
Min.
Typ.
4
18
Min.
Max.
10
Units
pF
pF
Note:
4. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
C
PD
×
V
CC
×
f
IN
×
I
CC
Average operating current can be obtained by the eqation: I
CC(opr.)
=
--------------------------------------------------------
-
4
(
per
,
Gate
)
©1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.4.0
www.fairchildsemi.com
4
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
