74LVX00 — Low Voltage Quad 2-Input NAND Gate
February 2008
74LVX00
Low Voltage Quad 2-Input NAND Gate
Features
■
Input voltage level translation from 5V to 3V
■
Ideal for low power/low noise 3.3V applications
■
Guaranteed simultaneous switching noise level and
General Description
The LVX00 contains four 2-input NAND gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
dynamic threshold performance
Ordering Information
Order
Number
74LVX00M
74LVX00SJ
74LVX00MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
©1993 Fairchild Semiconductor Corporation
74LVX00 Rev. 1.4.0
www.fairchildsemi.com
74LVX00 — Low Voltage Quad 2-Input NAND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
V
I
I
OK
Supply Voltage
Parameter
DC Input Diode Current, V
I
=
–0.5V
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
Rating
–0.5V to +7.0V
–20mA
–0.5V to 7V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±25mA
±50mA
–65°C to +150°C
180mW
V
O
I
O
DC Output Voltage
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current
T
STG
Storage Temperature
P
Power Dissipation
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
Parameter
Rating
2.0V to 3.6V
0V to 5.5V
0V to V
CC
–40°C to +85°C
0ns/V to 100ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74LVX00 Rev. 1.4.0
www.fairchildsemi.com
2
74LVX00 — Low Voltage Quad 2-Input NAND Gate
DC Electrical Characteristics
T
A
=
+25°C
Symbol
V
IH
T
A
=
–40°C to
+85°C
Min.
1.5
2.0
2.4
Parameter
HIGH Level Input
Voltage
V
CC
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
Conditions
Min.
1.5
2.0
2.4
Typ. Max.
Max.
Units
V
V
IL
LOW Level Input
Voltage
0.5
0.8
0.8
V
IN
=
V
IL
or V
IH
,
I
OH
=
–50µA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–50µA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–4mA
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
±0.1
2.0
2.0
3.0
1.9
2.9
2.48
0.5
0.8
0.8
V
V
OH
HIGH Level Output
Voltage
V
V
OL
LOW Level Output
Voltage
2.0
3.0
V
IN
=
V
IL
or V
IH
,
I
OL
=
50µA
V
IN
=
V
IL
or V
IH
,
I
OL
=
50µA
V
IN
=
V
IL
or V
IH
,
I
OL
=
4mA
0.1
0.1
0.44
±1.0
20.0
V
I
IN
I
CC
Input Leakage
Current
Quiescent Supply
Current
3.6
3.6
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
µA
µA
Noise Characteristics
(2)
T
A
=
25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
3.3
3.3
3.3
3.3
C
L
(pF)
50
50
50
50
Typ.
0.3
–0.3
Limit
0.5
–0.5
2.0
0.8
Units
V
V
V
V
Note:
2. Input t
r
=
t
f
=
3ns
©1993 Fairchild Semiconductor Corporation
74LVX00 Rev. 1.4.0
www.fairchildsemi.com
3
74LVX00 — Low Voltage Quad 2-Input NAND Gate
AC Electrical Characteristics
T
A
=
+25°C
Symbol
t
PLH
, t
PHL
T
A
=
–40°C to
+85°C
Min.
1.0
1.0
1.0
1.0
Parameter
Propagation Delay Time
V
CC
(V)
2.7
3.3 ± 0.3
C
L
(pF)
15
50
15
50
50
Min.
Typ.
5.4
7.9
4.1
6.6
Max.
10.1
13.6
6.2
9.7
1.5
1.5
Max.
12.5
16.0
7.5
11.0
1.5
1.5
Units
ns
t
OSLH
, t
OSHL
Output to Output Skew
(3)
2.7
3.3
ns
Note:
3. Parameter guaranteed by design t
OSLH
=
|t
PLHm
–t
PLHn
|, t
OSHL
=
|t
PHLm
–t
PHLn
|
Capacitance
T
A
=
+25°C
Symbol
C
IN
C
PD
T
A
=
–40°C to
+85°C
Max.
10
Parameter
Input Capacitance
Power Dissipation Capacitance
(4)
Min.
Typ.
4
19
Min.
Max.
10
Units
pF
pF
Note:
4. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
C
PD
×
V
CC
×
f
IN
×
I
CC
Average operating current can be obtained by the eqation: I
CC(opr.)
=
--------------------------------------------------------
-
4
(
per
,
Gate
)
©1993 Fairchild Semiconductor Corporation
74LVX00 Rev. 1.4.0
www.fairchildsemi.com
4
74LVX00 — Low Voltage Quad 2-Input NAND Gate
Physical Dimensions
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
PIN ONE
INDICATOR
1
7
1.70
1.27
1.27
(0.33)
0.51
0.35
0.25
M
LAND PATTERN RECOMMENDATION
C B A
1.75 MAX
1.50
1.25
0.25
0.10
C
0.10 C
SEE DETAIL A
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
X 45°
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1993 Fairchild Semiconductor Corporation
74LVX00 Rev. 1.4.0
www.fairchildsemi.com
5
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