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74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear
January 2008
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
Features
■
Input and output interface capability to systems at
■
■
■
■
■
General Description
The LVTH273 is a high-speed, low-power positive-edge-
triggered octal D-type flip-flop featuring separate D-type
inputs for each flip-flop. A buffered Clock (CP) and Clear
(CLR) are common to all flip-flops.
The state of each D-type input, one setup time before
the positive clock transition, is transferred to the corre-
sponding flip-flop's output.
The LVTH273 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal flip-flops are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH273 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintain-
ing low power dissipation.
5V V
CC
Bushold on the data inputs eliminate the need for
external pull-up resistors to hold unused inputs
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 273
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
>
2000V
– Machine model
>
200V
– Charged-device model
>
1000V
Ordering Information
Order Number
74LVTH273WM
74LVTH273SJ
74LVTH273MTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74LVTH273 Rev. 1.6.0
www.fairchildsemi.com
74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D
0
–D
7
CP
CLR
O
0
–O
7
Description
Data Inputs
Clock Pulse Input
Clear
Outputs
Truth Table
Functional Description
The LVTH273 consists of eight positive-edge-triggered
flip-flops with individual D-type inputs. The buffered
Clock and Clear are common to all flip-flops. The eight
flip-flops will store the state of their individual D-type
inputs that meet the setup and hold time requirements
on the LOW-to-HIGH Clock (CP) transition. When the
Clock is either HIGH or LOW, the D-input signal has no
effect at the output. When the Clear (CLR) is LOW, all
Outputs will be forced LOW.
D
n
H
L
X
X
Inputs
CP
CLR
H
H
Outputs
O
n
H
L
O
o
L
H or L
X
H
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
O
o
=
Previous O
o
before HIGH-to-LOW of CP
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1999 Fairchild Semiconductor Corporation
74LVTH273 Rev. 1.6.0
www.fairchildsemi.com
2
74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
Parameter
Rating
–0.5V to +4.6V
–0.5V to +7.0V
–0.5V to +7.0V
–50mA
–50mA
64mA
128mA
±64mA
±128mA
–65°C to +150°C
DC Output Voltage
,
Output in HIGH or LOW State
(1)
DC Input Diode Current, V
I
<
GND
DC Output Diode Current, V
O
<
GND
DC Output Current, V
O
>
V
CC
Output at HIGH State
Output at LOW State
I
CC
I
GND
T
STG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
1. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
I
OH
I
OL
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Parameter
Min
2.7
0
Max
3.6
5.5
–32
64
Units
V
V
mA
mA
°C
ns/V
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
©1999 Fairchild Semiconductor Corporation
74LVTH273 Rev. 1.6.0
www.fairchildsemi.com
3
74LVTH273 — Low Voltage Octal D-Type Flip-Flop with Clear
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
T
A
=
–40°C to +85°C
Conditions
I
I
=
–18mA
V
O
≤
0.1V or
V
O
≥
V
CC
– 0.1V
I
OH
=
–100µA
I
OH
=
–8mA
I
OH
=
–32mA
I
OL
=
100µA
I
OL
=
24mA
I
OL
=
16mA
I
OL
=
32mA
I
OL
=
64mA
V
CC
– 0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
–75
500
–500
10
±1
–5
1
±100
0.19
5
0.2
µA
mA
mA
mA
µA
µA
µA
V
2.0
0.8
Min.
Typ.
(2)
Max.
–1.2
Units
V
V
V
V
V
OL
Output LOW Voltage
2.7
3.0
I
I(HOLD)
I
I(OD)
I
I
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
3.0
3.0
3.6
3.6
3.6
0
3.6
3.6
3.6
V
I
=
0.8V
V
I
=
2.0V
(3)
(4)
V
I
=
5.5V
V
I
=
0V or V
CC
V
I
=
0V
V
I
=
V
CC
0V
≤
V
I
or V
O
≤
5.5V
Outputs HIGH
Outputs LOW
One Input at V
CC
– 0.6V,
Other Inputs at V
CC
or
GND
I
OFF
I
CCH
I
CCL
∆I
CC
Power Off Leakage Current
Power Supply Current
Power Supply Current
Increase in Power Supply
Current
(5)
Notes:
2. All typical values are at V
CC
=
3.3V, T
A
=
25°C.
3. An external driver must source at least the specified current to switch from LOW-to-HIGH.
4. An external driver must sink at least the specified current to switch from HIGH-to-LOW.
5. This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
©1999 Fairchild Semiconductor Corporation
74LVTH273 Rev. 1.6.0
www.fairchildsemi.com
4
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