74LVT240, 74LVTH240 — Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
January 2008
74LVT240, 74LVTH240
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
Features
■
Input and output interface capability to systems at
■
General Description
The LVT240 and LVTH240 are inverting octal buffers
and line drivers designed to be employed as memory
address drivers, clock drivers and bus oriented transmit-
ters or receivers which provides improved PC board
density.
The LVTH240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal buffers and line drivers are designed for low-
voltage (3.3V) V
CC
applications, but with the capability to
provide a TTL interface to a 5V environment. The LVT240
and LVTH240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
■
■
■
■
■
■
5V V
CC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH240),
also available without bushold feature (74LVT240)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 240
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
>
2000V
– Machine model
>
200V
– Charged-device model
>
1000V
Ordering Information
Order Number
74LVT240WM
74LVT240SJ
74LVT240MSA
74LVT240MTC
74LVTH240WM
74LVTH240SJ
74LVTH240MSA
74LVTH240MTC
Package
Number
M20B
M20D
MSA20
MTC20
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74LVT240, 74LVTH240 Rev. 1.5.0
www.fairchildsemi.com
74LVT240, 74LVTH240 — Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
Connection Diagrams
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Inputs
3-STATE Outputs
Description
3-STATE Output Enable Inputs
Truth Tables
Inputs
OE
1
L
L
H
I
n
L
H
X
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Inputs
OE
2
L
L
H
I
n
L
H
X
Outputs
(Pins 3, 5, 7, 9)
H
L
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
©1999 Fairchild Semiconductor Corporation
74LVT240, 74LVTH240 Rev. 1.5.0
www.fairchildsemi.com
2
74LVT240, 74LVTH240 — Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
Supply Voltage
DC Input Voltage
DC Output Voltage
Output in 3-STATE
Parameter
Rating
–0.5V to +4.6V
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to +7.0V
–50mA
–50mA
64mA
128mA
±64mA
±128mA
–65°C to +150°C
Output in HIGH or LOW State
(1)
I
IK
I
OK
I
O
DC Input Diode Current, V
I
<
GND
DC Output Diode Current, V
O
<
GND
DC Output Current, V
O
>
V
CC
Output at HIGH State
Output at LOW State
I
CC
I
GND
T
STG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
1. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
I
OH
I
OL
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Parameter
Min
2.7
0
Max
3.6
5.5
–32
64
Units
V
V
mA
mA
°C
ns/V
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
©1999 Fairchild Semiconductor Corporation
74LVT240, 74LVTH240 Rev. 1.5.0
www.fairchildsemi.com
3
74LVT240, 74LVTH240 — Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
T
A
=
–40°C to +85°C
Conditions
I
I
=
–18mA
V
O
≤
0.1V or
V
O
≥
V
CC
– 0.1V
I
OH
=
–100µA
I
OH
=
–8mA
I
OH
=
–32mA
I
OL
=
100µA
I
OL
=
24mA
I
OL
=
16mA
I
OL
=
32mA
I
OL
=
64mA
2.0
0.8
V
CC
–0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
–75
500
–500
10
±1
–5
1
±100
±100
–5
5
10
0.19
5
0.19
0.19
0.2
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
µA
µA
µA
V
Min.
Typ.
(2)
Max. Units
–1.2
V
V
V
V
V
OL
Output LOW Voltage
2.7
3.0
I
I(HOLD)
I
I(OD)
I
I
(3)
Bushold Input Minimum
Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
3.0
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
I
=
0.8V
V
I
=
(4)
(5)
2.0V
(3)
V
I
=
5.5V
V
I
=
0V or V
CC
V
I
=
0V
V
I
=
V
CC
0V
≤
V
I
or V
O
≤
5.5V
V
O
=
0.5V to 3.0V,
V
I
=
GND or V
CC
V
O
=
0.5V
V
O
=
3.0V
V
CC
<
V
O
≤
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
≤
V
O
≤
5.5V,
Outputs Disabled
One Input at V
CC
– 0.6V,
Other Inputs at V
CC
or
GND
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
+
I
CCH
I
CCL
I
CCZ
I
CCZ
+
∆I
CC
Power Off Leakage Current
Power up/down 3-STATE
Output Current
3-STATE Output Leakage
Current
3-STATE Output Leakage
Current
3-STATE Output Leakage
Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply
Current
(6)
Notes:
2. All typical values are at V
CC
=
3.3V, T
A
=
25°C.
3. Applies to bushold versions only (74LVTH240).
4. An external driver must source at least the specified current to switch from LOW-to-HIGH.
5. An external driver must sink at least the specified current to switch from HIGH-to-LOW.
6. This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
©1999 Fairchild Semiconductor Corporation
74LVT240, 74LVTH240 Rev. 1.5.0
www.fairchildsemi.com
4
74LVT240, 74LVTH240 — Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
Dynamic Switching Characteristics
(7)
Conditions
Symbol
V
OLP
V
OLV
T
A
=
25°C
Min.
Typ.
0.8
–0.8
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
V
CC
(V)
3.3
3.3
C
L
=
50pF, R
L
=
500Ω
(8)
Max.
Units
V
V
(8)
Notes:
7. Characterized in SOIC package. Guaranteed parameter, but not tested.
8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
=
–40°C to +85°C
C
L
=
50pF, R
L
=
500Ω
V
CC
=
3.3V ±0.3V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
, t
OSLH
Output to Output Skew
(10)
Notes:
9. All typical values are at V
CC
=
3.3V, T
A
=
25°C.
10. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Output Disable Time
Output Enable Time
V
CC
=
2.7V
Min.
1.1
1.3
1.1
1.4
2.0
1.8
Parameter
Propagation Delay, Data to Output
Min.
1.1
1.3
1.1
1.4
2.0
1.8
Typ.
(9)
Max.
3.8
4.0
4.6
4.4
4.5
4.3
1.0
Max.
4.6
4.2
5.6
5.1
4.7
4.3
1.0
Units
ns
ns
ns
ns
Capacitance
(11)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
CC
=
0V, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
Typical
3
6
Units
pF
pF
Note:
11. Capacitance is measured at frequency f
=
1MHz, per MIL-STD-883, Method 3012.
©1999 Fairchild Semiconductor Corporation
74LVT240, 74LVTH240 Rev. 1.5.0
www.fairchildsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
