Ordering number : EN8300A
LC875832A
LC875824A
LC875816A
Overview
CMOS IC
ROM 32K/24K/16K byte, RAM 1024 byte on-chip
8-bit 1-chip Microcontroller
The SANYO LC875832A/24A/16A are 8-bit microcomputers that, centered around a CPU running at a minimum bus
cycle time of 100ns, integrate on a single chip a number of hardware features such as 32K/24K/16K-byte ROM
1024-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter
(may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a
time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception
capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD
converter, two 12-bit PWM channels, a system clock frequency divider, ROM correction function , and a 23-source
10-vector interrupt feature.
Features
ROM
•
32768
×
8-bits (LC875832A)
•
24576
×
8-bits (LC875824A)
•
16384
×
8-bits (LC875816A)
RAM
•
1024
×
9 bits (LC875832A/24A/16A)
Minimum Bus Cycle
•
100ns (10MHz)
VDD=3.0 to 3.6V
•
125ns (8MHz)
VDD=2.5 to 3.6V
•
500ns (2MHz)
VDD=2.2 to 3.6V
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
•
300ns (10MHz)
VDD=3.0 to 3.6V
•
375ns (8MHz)
VDD=2.5 to 3.6V
•
1.5µs (2MHz)
VDD=2.2 to 3.6V
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.05
83006 / 42706HKIM No.8300-1/23
LC875832A/24A/16A
Ports
•
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
•
Normal withstand voltage input ports
•
Dedicated oscillator ports
•
Reset pins
•
Power pins
46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
Timers
•
Timer 0 : 16-bit timer/counter with a capture register
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×
2 channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3 : 16-bit counter (with a 16-bit capture register)
•
Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs)
Mode 1 : 8-bit PWM with an 8-bit prescaler
×
2-channels
Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the
lower-order 8-bits)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as PWM)
•
Timer 4 : 8-bit timer with a 6-bit prescaler
•
Timer 5 : 8-bit timer with a 6-bit prescaler
•
Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz)
2) Can generate output real-time
SIO
•
SIO0 : 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle =4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
•
SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
UART
•
Full duplex
•
7/8/9 bit data bits selectable
•
1 stop bit (2-bit in continuous data transmission)
•
Built-in baudrate generator
No.8300-2/23
LC875832A/24A/16A
AD Converter : 8-bits
×
11-channels
PWM : Multifrequency 12-bit PWM
×
2-channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
•
Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog Timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
•
23 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer0/base timer1
T0H
T1L/T1H
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/T6/T7
Port 0/T4/T5/PWM2, PWM3
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels : 512 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
•
16-bits
×
8-bits
(5 tCYC execution time)
•
24-bits
×
16-bits
(12 tCYC execution time)
•
16-bits
÷
8-bits
(8 tCYC execution time)
•
24-bits
÷
16-bits
(12 tCYC execution time)
Oscillation Circuits
•
RC oscillation circuit (internal) :
•
CF oscillation circuit :
•
Crystal oscillation circuit :
For system clock
For system clock, with internal Rf
For low-speed system clock, with internal Rf
System Clock Divider Function
•
Can run on low current.
The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and
76.8µs (at a main clock rate of 10MHz).
No.8300-3/23
LC875832A/24A/16A
Standby Function
•
HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
•
HOLD mode : Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
•
X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the
base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
ROM Correction Function
•
Executes the correction program on detection of a match with the program counter value.
•
Correction program area size : 128 bytes
Package Form
•
QIP64E (14
×
14):
•
TQFP64 (10
×
10):
•
TQFP64J (10
×
10):
•
TQFP64J (7
×
7):
•
VQFN64 (10
×
10):
Development Tools
•
Evaluation chip :
•
Emulator :
Lead-free type
Lead-free type
Lead-free type
Lead-free type
Lead-free type
LC87EV690
EVA62S + ECB876600D + SUB875800 + POD64QFP or POD64SQFP
(* Tools for VQFN64 (10
×
10), TQFP64J (7
×
7) version of PODs to be determined)
No.8300-4/23
LC875832A/24A/16A
Package Dimensions
unit : mm
3159A
17.2
14.0
48
49
33
32
49
14.0
17.2
Package Dimensions
unit : mm
3296
12.0
0.8
10.0
48
33
32
10.0
64
17
1
16
0.2
64
1
0.8
(1.0)
(2.7)
17
16
0.35
0.15
(1.25)
0.5
0.15
3.0max
1.2max
0.1
0.1
(1.0)
SANYO : QIP64E(14X14)
SANYO : TQFP64(10X10)
Package Dimensions
unit : mm
3310
12.0
Package Dimensions
unit : mm
3289
9.0
0.5
10.0
48
49
33
32
48
49
10.0
12.0
33
32
7.0
64
1
(1.25)
0.5
16
0.18
17
64
0.125
17
1
0.4
16
0.16
0.125
(0.5)
1.2 MAX
(1.0)
0.1
SANYO : TQFP64J(10X10)
1.2max
0.1
(1.0)
SANYO : TQFP64J(7X7)
9.0
No.8300-5/23
0.5
7.0
12.0
0.5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
