HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7015S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35ns (max.)
— Commercial: 12/15/17/20/25/35ns (max.)
• Low-power operation
— IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7015 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
• Interrupt and Busy Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• TTL-compatible, single 5V (±10%) power supply
• Available in ceramic 68-pin PGA, 68-pin PLCC, and an
80-pin TQFP
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7015 is a high-speed 8K x 9 Dual-Port Static
RAMs. The IDT7015 is designed to be used as stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 18-bit-or-more word systems. Using the IDT
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
CE
L
W
L
CE
R
R/
W
R
I/O
0L
- I/O
8L
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
13
(1,2)
A
12L
A
0L
MEMORY
ARRAY
Address
Decoder
A
12R
A
0R
13
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
INT
R
SEM
L
INT
L
(2)
M/
S
(2)
2954 drw 01
NOTES:
1. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2954/2
6.12
1
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
The IDT7015 is packaged in a ceramic 68-pin PGA, a 64-
pin PLCC and an 80-pin TQFP (Thin Quad FlatPack). Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level
of performance and reliability.
PIN CONFIGURATIONS
(1,2)
I/O
1L
I/O
0L
I/O
8L
SEM
L
4
W
L
R/
6
5
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
8
7
3
N/C
N/C
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
(3)
OE
L
CE
L
IDT7015
(8K x 9)
J68-1
PLCC
TOP VIEW
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
BUSY
R
INT
R
51
50
49
48
47
46
45
GND
M/
S
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
0R
A
1R
A
2R
A
3R
A
4R
I/O
7R
I/O
8R
SEM
R
N/C
N/C
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
OE
R
W
R
CE
R
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not imply orientation of Part-Mark.
R/
2954 drw 02
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2954 tbl 01
CE
L
R/
W
L
OE
L
A
0L
– A
12L
I/O
0L
– I/O
8L
CE
R
R/
W
R
OE
R
A
0R
– A
12R
I/O
0R
– I/O
8R
SEM
L
INT
L
BUSY
L
M/
S
V
CC
SEM
R
INT
R
BUSY
R
GND
6.12
2
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CON'T.)
(1,2)
I/O
0L
I/O
8L
I/O
1L
R/
L
SEM
L
A
12L
A
11L
A
10L
OE
L
V
CC
CE
L
W
NC
A
9L
A
8L
NC
NC
A
7L
A
6L
INDEX
79
78
77
76
70
69
68
67
75
66
65
64
63
62
72
71
80
74
73
61
NC
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
NC
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
NC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
IDT7015
(8K X 9)
PN-80
TQFP
TOP VIEW
(3)
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
22
23
21
27
28
30
31
33
34
26
35
37
38
36
24
25
29
32
39
40
20
41
I/O
7R
I/O
8R
R/
R
NC
GND
NC
NC
A
11R
A
10R
A
9R
A
8R
SEM
R
A
12R
A
7R
CE
R
OE
R
A
6R
A
5R
NC
W
NC
2954 drw 03
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/
S
45
INT
L
40
INT
R
38
A
1R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
10
43
41
39
37
GND
BUSY
R
A
0R
A
2R
09
08
57
56
A
11L
A
10L
59
58
V
CC
A
12L
IDT7015
(8K x 9)
G68-1
68-PIN PGA
TOP VIEW
(3)
07
28
29
A
11R
A
10R
26
27
GND A
12R
24
N/C
25
N/C
23
61
60
06
N/C
N/C
63
05
SEM
L
CE
L
OE
L
R/
W
L
64
62
65
04
SEM
R
20
22
CE
R
03
67
66
I/O
0L
I/O
8L
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
3L
I/O
5L
A
B
C
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
8
I/O
6L
V
CC
D
E
10
12
14
16
I/O
0R
I/O
2R
I/O
3R
I/O
5R
F
G
H
J
OE
R
21
R/
R
W
02
18
19
I/O
7R
I/O
8R
17
I/O
6R
K
L
2954 drw 04
01
NOTES:
1. All Vcc must be connected to power supply.
2. All GND must be connected to ground supply.
3. This text does not imply orientation of Part-Mark.
INDEX
6.12
3
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
H
L
L
X
R/
W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
I/O
0-8
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
Mode
NOTE:
1. Condition: A
0L
— A
12L
is not equal to A
0R
— A
12R.
2954 tbl 02
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL
Inputs
Outputs
(1)
CE
H
H
L
R/
W
OE
L
X
X
SEM
L
L
L
I/O
0-8
DATA
OUT
DATA
IN
—
Write I/O
0
into Semaphore Flag
Not Allowed
Mode
Read Semaphore Flag Data Out (I/O
0-8
)
u
X
H
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0-8
. These eight semaphores are addressed by A
0
- A
2
.
2954 tbl 03
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
Military
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125
–55 to +125
50
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2954 tbl 05
T
A
T
BIAS
T
STG
I
OUT
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
(2)
0.8
V
V
V
V
2954 tbl 06
NOTES:
2954 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.5V.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz) TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2954 tbl 07
NOTES:
1.
This parameter is determined by device characteristics but is not
production tested.
2.
3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V .
6.12
4
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
7015S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
Min.
—
—
—
2.4
Max.
10
10
0.4
—
—
—
—
2.4
7015L
Min.
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2954 tbl 08
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
NOTE:
1. At Vcc < 2.0V, Input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 5.0V
±
10%)
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
I
SB1
Standby Current
(Both Ports — TTL
Level Inputs)
I
SB2
Standby Current
(One Port — TTL
Level Inputs)
I
SB3
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
Test
Condition
Version
MIL.
COM’L.
MIL.
COM’L.
MIL.
COM’L.
MIL.
COM’L.
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
7015X12
Com'l. Only
Typ.
(2)
Max.
—
—
170
170
—
—
25
25
—
—
105
105
—
—
1.0
0.2
—
—
100
100
—
—
325
275
—
—
70
60
—
—
200
170
—
—
15
5
—
—
180
150
7015X15
Com'l. Only
Typ.
(2)
Max.
—
—
170
170
—
—
25
25
—
—
105
105
—
—
1.0
0.2
—
—
100
100
—
—
310
260
—
—
60
50
—
—
190
160
—
—
15
5
—
—
170
140
7015X17
Com'l. Only
Typ.
(2)
Max. Unit
—
—
170
170
—
—
25
25
—
—
105
109
—
—
1.0
0.2
—
—
100
100
—
—
310
260
—
—
60
50
—
—
190
160
—
—
15
5
—
—
170
140
mA
mA
mA
mA
mA
CE
= V
IL
, Outputs Open
SEM
= V
IH
f = f
MAX(3)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX(3)
Active Port Outputs Open
f = f
MAX(3)
SEM
R
=
SEM
L
= V
IH
CE
"A"
=V
IL
and
CE
"B"
= V
IH(5)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V
Active Port Outputs Open,
f = f
MAX(3)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
MIL.
COM’L.
mA
NOTES:
2954 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. I
CCDC
= 120mA(typ.)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/t
RC,
and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite of port "A".
6.12
5
NXP MCU
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