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IDT71V124SA12YG8: 产品描述Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32; 产品类别存储存储; 文件大小79KB，共8页; 制造商IDT (Integrated Device Technology); 标准

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IDT71V124SA12YG8概述

Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32

IDT71V124SA12YG8规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	SOJ
包装说明	SOJ,
针数	32
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	12 ns
JESD-30 代码	R-PDSO-J32
JESD-609代码	e3
长度	20.955 mm
内存密度	1048576 bit
内存集成电路类型	STANDARD SRAM
内存宽度	8
功能数量	1
端子数量	32
字数	131072 words
字数代码	128000
工作模式	ASYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	128KX8
封装主体材料	PLASTIC/EPOXY
封装代码	SOJ
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	3.683 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3.15 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	MATTE TIN
端子形式	J BEND
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	10.16 mm
Base Number Matches	1

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3.3V CMOS Static RAM

1 Meg (128K x 8-Bit)

Center Power &

Ground Pinout

◆

IDT71V124SA

Features

◆

128K x 8 advanced high-speed CMOS static RAM

JEDEC revolutionary pinout (center power/GND) for

reduced noise

Equal access and cycle times

– Commercial: 10/12/15ns

– Industrial: 12/15ns

One Chip Select plus one Output Enable pin

Inputs and outputs are LVTTL-compatible

Single 3.3V supply

Low power consumption via chip deselect

Available in a 32-pin 300- and 400-mil Plastic SOJ, and

32-pin Type II TSOP packages.

The IDT71V124 is a 1,048,576-bit high-speed static RAM organized

as 128K x 8. It is fabricated using high-performance, high-reliability CMOS

technology. This state-of-the-art technology, combined with innovative

circuit design techniques, provides a cost-effective solution for high-speed

memory needs. The JEDEC center power/GND pinout reduces noise

generation and improves system performance.

The IDT71V124 has an output enable pin which operates as fast as

5ns, with address access times as fast as 10ns available. All bidirectional

inputs and outputs of the IDT71V124 are LVTTL-compatible and operation

is from a single 3.3V supply. Fully static asynchronous circuitry is used;

no clocks or refreshes are required for operation.

Description

Functional Block Diagram

•

ADDRESS

DECODER

•

1,048,576-BIT

MEMORY ARRAY

I/O

- I/O

I/O CONTROL

CONTROL

LOGIC

3873 drw 01

FEBRUARY 2013

DSC-3873/11

IDT71V124SA12YG8相似产品对比

	IDT71V124SA12YG8	IDT71V124SA12YGI	IDT71V124SA12YG	IDT71V124SA10YG8	IDT71V124SA15YGI8	IDT71V124SA15YGI	IDT71V124SA15YG	IDT71V124SA15YG8
描述	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32	Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32	Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32	Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32	Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32
是否无铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ
包装说明	SOJ,	SOJ, SOJ32,.44	SOJ, SOJ32,.44	SOJ,	SOJ,	SOJ, SOJ32,.44	SOJ, SOJ32,.44	SOJ,
针数	32	32	32	32	32	32	32	32
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	12 ns	12 ns	12 ns	10 ns	15 ns	15 ns	15 ns	15 ns
JESD-30 代码	R-PDSO-J32	R-PDSO-J32	R-PDSO-J32	R-PDSO-J32	R-PDSO-J32	R-PDSO-J32	R-PDSO-J32	R-PDSO-J32
JESD-609代码	e3	e3	e3	e3	e3	e3	e3	e3
长度	20.955 mm	20.955 mm	20.955 mm	20.955 mm	20.955 mm	20.955 mm	20.955 mm	20.955 mm
内存密度	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit
内存集成电路类型	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
内存宽度	8	8	8	8	8	8	8	8
功能数量	1	1	1	1	1	1	1	1
端子数量	32	32	32	32	32	32	32	32
字数	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words
字数代码	128000	128000	128000	128000	128000	128000	128000	128000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	70 °C	85 °C	70 °C	70 °C	85 °C	85 °C	70 °C	70 °C
组织	128KX8	128KX8	128KX8	128KX8	128KX8	128KX8	128KX8	128KX8
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	260	260	260	260	260	260	260	260
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.683 mm	3.683 mm	3.683 mm	3.683 mm	3.683 mm	3.683 mm	3.683 mm	3.683 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
端子面层	MATTE TIN	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	MATTE TIN	MATTE TIN	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	MATTE TIN
端子形式	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND
端子节距	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	30	30	30	30
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Base Number Matches	1	1	1	1	1	1	1	1

IDT71V124SA12YG8

IDT71V124SA12YG8概述

IDT71V124SA12YG8规格参数

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