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Intel
815 Chipset Family:
82815P/82815EP Memory
Controller Hub (MCH)
For Use with Universal Socket 370
Datasheet
September 2001
Document Number:
290720-001
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Information in this document is provided in connection with Intel
®
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
815 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
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*Other names and brands may be claimed as the property of others.
Copyright 2001, Intel Corporation
©
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82815P/82815EP MCH Datasheet
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Contents
1
Introduction ........................................................................................................................11
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
Related Documents ..............................................................................................12
The Intel
815P Chipset........................................................................................13
®
Intel 82815P MCH Overview ...............................................................................15
Host Interface........................................................................................................16
System Memory Interface .....................................................................................16
AGP Interface .......................................................................................................17
Hub Interface ........................................................................................................17
System Clocking ...................................................................................................18
MCH Power Delivery.............................................................................................18
Signal Description..............................................................................................................19
2.1
2.2
2.3
Host Interface Signals...........................................................................................20
System Memory Interface Signals ........................................................................21
AGP Interface Signals...........................................................................................22
2.3.1
AGP Addressing Signals .......................................................................22
2.3.2
AGP Flow Control Signals .....................................................................23
2.3.3
AGP Status Signals ...............................................................................23
2.3.4
AGP Clocking Signals (Strobes) ...........................................................24
2.3.5
AGP FRAME# Signals ..........................................................................25
Hub Interface Signals............................................................................................27
Power Signals .......................................................................................................27
Clock Signals ........................................................................................................28
MCH Power-Up/Reset Strap Options ...................................................................28
Intel® 82815 to 82815P Signal Name Changes ...................................................29
2.4
2.5
2.6
2.7
2.8
3
Configuration Registers .....................................................................................................31
3.1
3.2
Register Nomenclature and Access Attributes .....................................................31
PCI Configuration Space Access..........................................................................32
3.2.1
PCI Bus Configuration Mechanism .......................................................32
3.2.2
Logical PCI Bus #0 Configuration Mechanism ......................................33
3.2.3
Primary PCI (PCI0) and Downstream Configuration Mechanism .........33
3.2.4
MCH Register Introduction ....................................................................33
I/O Mapped Registers ...........................................................................................34
3.3.1
CONF_ADDR—Configuration Address Register ..................................34
3.3.2
CONF_DATA—Configuration Data Register ........................................35
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) ..........36
3.4.1
VID—Vendor Identification Register (Device 0) ....................................38
3.4.2
DID—Device Identification Register (Device 0).....................................38
3.4.3
PCICMD—PCI Command Register (Device 0) .....................................39
3.4.4
PCISTS—PCI Status Register (Device 0).............................................40
3.4.5
RID—Revision Identification Register (Device 0)..................................41
3.4.6
SUBC—Sub-Class Code Register (Device 0).......................................41
3.4.7
BCC—Base Class Code Register (Device 0)........................................41
3.3
3.4
82815P/82815EP MCH Datasheet
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3.5
MLT—Master Latency Timer Register (Device 0).................................42
HDR—Header Type Register (Device 0) ..............................................42
APBASE—Aperture Base Configuration Register (Device 0: AGP
Mode Only) ............................................................................................42
3.4.11 SVID—Subsystem Vendor Identification Register (Device 0) ...............44
3.4.12 SID—Subsystem Identification Register (Device 0) ..............................44
3.4.13 CAPPTR—Capabilities Pointer (Device 0)............................................44
3.4.14 GMCHCFG—MCH Configuration Register (Device 0)..........................45
3.4.15 APCONT—Aperture Control (Device 0) ................................................47
3.4.16 DRP—DRAM Row Population Register (Device 0)...............................48
3.4.17 DRAMT—DRAM Timing Register (Device 0)........................................49
3.4.18 DRP2—DRAM Row Population Register 2 (Device 0)..........................50
3.4.19 FDHC—Fixed DRAM Hole Control Register (Device 0)........................51
3.4.20 PAM—Programmable Attributes Map Registers (Device 0) .................51
3.4.21 SMRAM—System Management RAM Control Register (Device 0) .....56
3.4.22 MISCC—Miscellaneous Control Register (Device 0) ............................58
3.4.23 CAPID—Capability Identification (Device 0: AGP Mode Only).............60
3.4.24 BUFF_SC—System Memory Buffer Strength Control Register
(Device 0) ..............................................................................................61
3.4.25 BUFF_SC2—System Memory Buffer Strength Control Register 2
(Device 0) ..............................................................................................64
3.4.26 SM_RCOMP—System Memory R Compensation Control Register
(Device 0) ..............................................................................................65
3.4.27 SM—System Memory Control Register ................................................66
3.4.28 ACAPID—AGP Capability Identifier Register (Device 0: AGP Mode
Only) ......................................................................................................67
3.4.29 AGPSTAT—AGP Status Register (Device 0: AGP Mode Only) ..........68
3.4.30 AGPCMD—AGP Command Register (Device 0: AGP Mode Only) .....69
3.4.31 AGPCTRL—AGP Control Register (Device 0: AGP Mode Only).........70
3.4.32 APSIZE—Aperture Size (Device 0: AGP Mode Only) ...........................71
3.4.33 ATTBASE—Aperture Translation Table Base Register (Device 0:
AGP Mode Only) ...................................................................................72
3.4.34 AMTT—AGP Multi-Transaction Timer (Device 0: AGP Mode Only) ....73
3.4.35 LPTT—AGP Low Priority Transaction Timer Register (Device 0:
AGP Mode Only) ...................................................................................74
3.4.36 GMCHCFG—MCH Configuration Register (Device 0:
AGP Mode Only) ...................................................................................75
3.4.37 ERRCMD—Error Command Register (Device 0: AGP Mode Only) ....76
AGP/PCI Bridge Registers (Device 1: Visible in AGP Mode Only) ......................78
3.5.1
VID1—Vendor Identification Register (Device 1) ..................................79
3.5.2
DID1—Device Identification Register (Device 1)...................................79
3.5.3
PCICMD1—PCI-PCI Command Register (Device 1)............................80
3.5.4
PCISTS1—PCI-PCI Status Register (Device 1)....................................81
3.5.5
RID1—Revision Identification Register (Device 1)................................82
3.5.6
SUBC1—Sub-Class Code Register (Device 1).....................................82
3.5.7
BCC1—Base Class Code Register (Device 1)......................................82
3.5.8
MLT1—Master Latency Timer Register (Device 1)...............................83
3.5.9
HDR1—Header Type Register (Device 1) ............................................83
3.5.10 PBUSN—Primary Bus Number Register (Device 1) .............................83
3.5.11 SBUSN—Secondary Bus Number Register (Device 1) ........................84
3.5.12 SUBUSN—Subordinate Bus Number Register (Device 1) ...................84
3.5.13 SMLT—Secondary Master Latency Timer Register (Device 1) ............85
3.5.14 IOBASE—I/O Base Address Register (Device 1) .................................86
3.5.15 IOLIMIT—I/O Limit Address Register (Device 1) ..................................87
3.4.8
3.4.9
3.4.10
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82815P/82815EP MCH Datasheet
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3.5.16
3.5.17
3.5.18
3.5.19
3.5.20
3.5.21
3.5.22
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4.1
SSTS—Secondary PCI-PCI Status Register (Device 1) .......................88
MBASE—Memory Base Address Register (Device 1) ..........................89
MLIMIT—Memory Limit Address Register (Device 1)...........................90
PMBASE—Prefetchable Memory Base Address Register (Device 1) ..91
PMLIMIT—Prefetchable Memory Limit Address Register (Device 1) ...92
BCTRL—PCI-PCI Bridge Control Register (Device 1) ..........................93
ERRCMD1—Error Command Register (Device 1) ...............................95
Functional Description .......................................................................................................97
System Address Map............................................................................................97
4.1.1
Memory Address Ranges......................................................................98
4.1.2
Compatibility Area .................................................................................99
4.1.3
Extended Memory Area.......................................................................101
4.1.3.1
System Management Mode (SMM) Memory Range..........104
Memory Shadowing ............................................................................................104
I/O Address Space..............................................................................................105
4.3.1
MCH Decode Rules and Cross-Bridge Address Mapping ..................105
4.3.2
Address Decode Rules........................................................................105
4.3.2.1
AGP Interface Decode Rules.............................................106
4.3.2.2
Legacy VGA Ranges..........................................................107
Host Interface......................................................................................................109
4.4.1
Host Bus Device Support ....................................................................109
4.4.2
Special Cycles .....................................................................................111
System Memory DRAM Interface .......................................................................112
4.5.1
DRAM Organization and Configuration ...............................................112
4.5.1.1
Configuration Mechanism for DIMMs ................................113
4.5.1.2
DRAM Register Programming ...........................................114
4.5.2
DRAM Address Translation and Decoding..........................................114
4.5.3
DRAM Array Connectivity....................................................................115
4.5.4
SDRAMT Register Programming ........................................................116
4.5.5
SDRAM Paging Policy.........................................................................116
System Reset for the MCH .................................................................................116
System Clock Description ...................................................................................116
Power Management............................................................................................117
4.8.1
Specifications Supported.....................................................................117
Intel 82815P MCH Ballout .................................................................................119
Package Information...........................................................................................127
®
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5
Ballout and Package Information.....................................................................................119
5.1
5.2
6
Testability.........................................................................................................................129
6.1
6.2
XOR Tree Testability Algorithm Example ...........................................................130
6.1.1
Test Pattern Consideration for XOR Chains 3 and 4, and 7 and 8 .....130
XOR Tree Initialization ........................................................................................131
6.2.1
Chain [1:6] Initialization .......................................................................131
6.2.2
Chain [7:8] Initialization .......................................................................131
XOR Chain..........................................................................................................132
All Z .....................................................................................................................137
6.3
6.4
82815P/82815EP MCH Datasheet
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