HIGH SPEED SRAM with
HIGH SPEED SRAM with
REVOLUTIONARY PINOUT
REVOLUTIONARY PINOUT
REVOLUTIONARY PINOUT
AVAILABLE AS MILITARY
AVAILABLE AS MILITARY
SPECIFICATIONS
MILITARY
AVAILABLE AS
SPECIFICATIONS
•SMD 5962-95600
SPECIFICATIONS
•SMD 5962-95600
•SMD 5962-95613
•SMD 5962-95600
•SMD 5962-95613
•MIL-STD-883
•SMD 5962-95613
•MIL-STD-883
•MIL-STD-883
FEATURES
Austin Semiconductor, Inc.
Austin Semiconductor, Inc.
512K x 8 SRAM
PIN ASSIGNMENT
512K x 8 SRAM
PIN ASSIGNMENT
PIN ASSIGNMENT
512K x 8 SRAM
(Top View)
HIGH SPEED SRAM with
(Top View)
(Top View)
AS5C512K8
AS5C512K8
AS5C512K8
SRAM
SRAM
SRAM
36-Pin SOJ (DJ, ECJ & SOJ)
36-Pin SOJ (DJ, ECJ & SOJ)
36-Pin CLCC (EC)
36-Pin CLCC (EC)
FEATURES
• Ultra High Speed Asynchronous Operation
FEATURES
• Fully Static, No Clocks
• Ultra High Speed Asynchronous Operation
• Ultra High Speed Asynchronous Operation
• Multiple center power and ground pins for improved
• Fully Static, No Clocks
• Fully Static, No Clocks
noise immunity
power and ground pins for improved
• Multiple center
• Multiple center power and ground pins for improved
• Easy memory expansion with CE\ and OE\
noise immunity
noise immunity
•
options
Easy memory expansion with CE\ and OE\
• Easy memory expansion with CE\ and OE\
• All inputs and outputs are TTL-compatible
options
options
• Single +5V Power Supply +/- 10%
•
• All inputs and outputs are TTL-compatible
All inputs and outputs are TTL-compatible
• Data Retention Functionality Testing
•
• Single +5V Power Supply +/- 10%
Single +5V Power Supply +/- 10%
• Cost Efficient Plastic Packaging
•
• Data Retention Functionality Testing
Data Retention Functionality Testing
• Extended Testing Over -55ºC to +125ºC for plastics
•
• Cost Efficient Plastic Packaging
Cost Efficient Plastic Packaging
• Plastic 36 pin PSOJ is fully compatible with the
•
• Extended Testing Over -55ºC
to
to
+125ºC for plastics
Extended Testing Over -55ºC
+125ºC for plastics
•
Ceramic 36 pin SOJ and offered in lead free finish
Plastic 36
36 pin PSOJ is fully compatible with the
pin PSOJ is fully compatible with the
• Plastic
• TSOPII in Copper Lead Frame for Superior Thermal
Ceramic 36
36 pin SOJ and offered in lead free finish
Ceramic
pin SOJ and offered in lead free finish
Performance
2
•
• 3.3V Future Offering
3.3V Future Offering
• RoHS Compliant Options Available
OPTIONS
OPTIONS
OPTIONS
•
• Timing
Timing
•
36-Pin
Flat Pack (F)
36-Pin
Flat Pack (F)
Timing
access
12ns
-12
12ns access
-12
12ns access
IS61C5128AL/AS
-12
-15
IS64C5128AL/AS
15ns access
15ns access
-15
15ns access
-15
17ns access
-17
17ns access
-17
17ns access
-17
-20
20ns access
20ns access
-20
20ns access
-20
-25
25ns access
25ns access
-25
HIGH SPEED (IS61/64C5128AL) PIN CONFIGURATION
25ns access
-25
-35
35ns access
35ns access
-35
35ns access
-35
-45
45ns access
36-Pin SOJ (400-mil)
44-Pin TSOP (Type II)
45ns access
-45
45ns access
-45
44-Pin TSOPII (DGC & DGCR)
•
• Operating Temperature Ranges
Operating Temperature Ranges
• Operating Temperature Ranges
o
/883C
Full Military (-55
o
to +125
o
C)
36
NC
1
Full Military (-55
o
C to +125
o
C)
C)
A0
/883C
/883C
Full Military (-55
o
C
C to +125
GENERAL DESCRIPTION
44
NC
NC
Military (-55
o
C to +125
o
C)
XT
35
A18
A1
2
GENERAL
12
DESCRIPTION
Military (-55
o
C to +125
o
C)
XT
XT
Military (-55
o
C to +125
o
C)
43
NC
NC
o
o
34
A17
A2
3
IT
Industrial (-40
The AS5C512K8
A0
3
Industrial (-40
o
C to +85
+85 C)
IT
IT
Industrial (-40
o
C
C to
o
C)
to +85
o
C)
The AS5C512K8
is a high speed SRAM. It offers flexibility in
is a high speed SRAM. It
42 NC
flexibility in
offers
33
A16
A3
4
41
A18
high-speed
A1 4
applications, with chip enable (CE\) and output
memory
high-speed
A2 5
applications, with chip enable (CE\) and output
memory
40
A17
32
A15
A4
5
• Package(s)
• Package(s)
enable (OE\) capabilities. These features can place the outputs in
39
A3
6
•
Ceramic LCC
Package(s)
enable (OE\) capabilities. These features can place
A16
outputs in
the
31
OE
CE
EC
6
A4
Ceramic LCC
EC
High-Z for
CE
7
additional flexibility in system design.
38 A15
37
OE
8
30
I/O7
I/O0
F
EC
7
Ceramic LCC
High-Z for additional flexibility in system design.
Ceramic Flatpack
Ceramic Flatpack
F
Writing to these devices is accomplished when write enable (WE\)
36
I/O7
I/O0
9
29
I/O6
I/O1
F
8
1
Ceramic Flatpack
Writing to these devices is accomplished when
35 I/O6
write enable (WE\)
I/O1
10
Plastic SOJ (Lead Free)
DJ
DJ
Plastic SOJ (Lead Free)*
and CE\ inputs are both LOW. Reading is accomplished when WE\
28
GND
V
DD
9
34
GND
VCC
11
Plastic SOJ
SOJ (attached formed lead)
DJ
(Lead Free)*
and CE\
HIGH and CE\ and OE\
Reading is accomplished when WE\
Ceramic SOJ (attached formed lead) ECJ
Ceramic
ECJ
33
12
VCC
GND
remains
inputs are both LOW.
go LOW.
27
V
DD
10
GND
Ceramic SOJ
ECJ
32
13
I/O5
I/O2
remains HIGH and CE\ and
can be supplied offering a reduced power
OE\ go LOW.
Ceramic SOJ
(attached formed lead)
SOJ
Ceramic SOJ
SOJ
26
11
I/O2
I/O5
As a option,
14
device
the
31
I/O3
2
Ceramic SOJ
also available, contact
DGC
SOJ
As
mode, allowing system
be supplied
meet low
I/O4
the
reduced power
Plastic TSOPII (44pin, 400mil)
I/O3
factory
25
12
I/O4
30
A14
WE
* Pb finish
standby
a option,
15
device can
designers to
offering a
standby power
2
16
A13
A5
allowing system designers to meet
29
* Pb finish also available, contact
WE
DGCR
standby mode,
This device operates from a single +5V
standby power
low
power supply
Plastic TSOPII (RoHS Compliant)
factory
24
13
A14
requirements.
17
28
A12
A6
23
14
A5
A13
requirements.
and outputs are fully TTL-compatible.
A11
+5V power supply
18
A7
• 2V data retention/low power
L
and all inputs
This device operates from a single
27
26
19
A10
A8
22
A6
L
L
15
A12
• 2V data retention/low power
• 2V data retention/low power
3
and all inputs and outputs are fully
convenience and reliability of the
The AS5C512K8DJ offers the
TTL-compatible.
NC
25
20
A9
21
16
A7
A11
Notes:
24
21
NC
NC
The AS5C512K8DJ offers
cost advantage
and reliability of the
AS5C512K8 SRAM and has the
the convenience
of a durable plastic.
For more products
A8 17
and information
A10
20
23
22
NC
NC
1. Pb finish also available, contact factory
AS5C512K8 SRAM and
footprint compatible with
a
36 pin
plastic.
The AS5C512K8DJ is
has the cost advantage of durable
CSOJ
For more products and information
NC
19
18
A9
please visit our web site at
2. Contact factory for Copper Lead Frame Products
The AS5C512K8DJ
5692-95600.
compatible with 36 pin CSOJ
package of the SMD
is footprint
please visit our web site at
3. Not available for parts in DGC & DGCR packages.
www.austinsemiconductor.com
package of the SMD 5692-95600.
AS5C512K8
AS5C512K8
Rev. 7.5 01/13
Rev. 7.0 05/08
AS5C512K8
Rev. 7.0 05/08
MARKING
MARKING
MARKING
www.austinsemiconductor.com
PIN DESCRIPTIONS
A0-A18
CE
Address Inputs
Chip Enable Input
1
1
1
Micross Components reserves the right to change products or specifications without notice.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C512K8
GENERAL DESCRIPTION
The AS5C512K8 is a high speed SRAM. It offers flexibility in
high-speed memory applications, with chip enable (CE\) and output
enable (OE\) capabilities. These features can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
As a option, the device can be supplied offering a reduced power
SRAM
Austin Semiconductor, Inc.
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +5V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5C512K8DJ offers the convenience and reliability of the
AS5C512K8 SRAM and has the cost advantage of a durable plastic.
The AS5C512K8DJ is footprint compatible with 36 pin CSOJ pack-
age of the SMD 5692-95600.
TSOPII with copper lead frame offers
superior thermal performance.
AS5C512K8
SRAM
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
INPUT BUFFER
ROW DECODER
1024 ROWS X
4096 COLUMNS
A0-A18
I/O
CONTROLS
4,194,304-BIT
MEMORY ARRAY
DQ8
DQ1
CE\
OE\
WE\
*POWER
DOWN
COLUMN DECODER
*On the low voltage Data Retention option.
PIN FUNCTIONS
A0 - A18
Address Inputs
Write Enable
Chip Enable
Output Enable
Data Inputs/Outputs
Power
Ground
No Connection
MODE
OE\ CE\ WE\
STANDBY
X
H
X
READ
L
L
H
NOT SELECTED H
L
H
WRITE
X
L
L
X = Don’t Care
TRUTH TABLE
WE\
I/O
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
CE\
OE\
I/O
0
- I/O
7
V
CC
V
SS
NC
AS5C512K8
Rev. 7.5 01/13
Micross Components reserves the right to change products or specifications without notice.
2
AS5C512K8
ABSOLUTE MAXIMUM RATINGS*
SRAM
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
Voltage on Vcc Supply Relative to Vss
Vcc ....................................................................-.5V to +7.0V is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
Storage Temperature (Plastic)......................-65°C to +150°C
operation section of this specification is not implied. Exposure
Storage Temperature (Ceramic)...................-55°C to +125°C
Short Circuit Output Current (per I/O)…........................20mA to absolute maximum rating conditions for extended periods
Voltage on any Pin Relative to Vss.................-.5V to Vcc+1V may affect reliability.
Maximum Junction Temperature**..............................+150°C ** Junction temperature depends upon package type, cycle time,
Power Dissipation ................................................................1W loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
A
< +125
o
C & -40
o
C < T
A
< +85
o
C ; Vcc = 5V +10%)
DESCRIPTION
Power Supply
Current: Operating
CONDITIONS
WE\=CE\<V
IL
; Vcc = MAX
f = MAX = 1/t
RC
Outputs Open
"L" Version Only
CE\ > V
IH
, All other inputs < V
IL
,
Vcc = MAX, f = 0,
Outputs Open
Power Supply
Current: Standby
"L" Version Only
CE\ > Vcc -0.2V; Vcc = MAX
V
IN
<Vss +0.2V or
V
IN
>Vcc -0.2V; f = 0
"L" Version Only
SYM
MAX
-12 -15 -17 -20 -25 -35 -45 UNITS NOTES
90
65
20
10
15
5
80
60
20
10
15
5
70
50
20
10
15
5
mA
mA
mA
mA
mA
mA
3
I
CCSP
100 100 100 90
I
CCLP
75
75
20
10
15
5
75
20
10
15
5
65
20
10
15
5
I
SBTSP
20
I
SBTLP
10
I
SBCSP
15
I
SBCLP
5
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
CONDITIONS
SYM
V
IH
V
IL
MIN
2.2
-0.5
-2
-2
2.4
---
4.5
MAX
Vcc +0.5
0.8
2
2
---
0.4
5.5
UNITS
V
V
μA
μA
V
V
V
NOTES
1
1, 2
0V < V
IN
< Vcc
Output(s) Disabled
0V < V
OUT
< Vcc
I
OH
= -4.0 mA
I
OL
= 8 mA
I
LI
I
LO
V
OH
V
OL
V
CC
1
1
1
CAPACITANCE
PARAMETER
Input Capacitance
Output Capactiance
CONDITIONS
T
A
= 25
o
C, f = 1MHz
V
IN
= 0
SYMBOL
C
I
Co
MAX
8
10
UNITS
pF
pF
NOTES
4
4
AS5C512K8
Rev. 7.5 01/13
Micross Components reserves the right to change products or specifications without notice.
3
AS5C512K8
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C < T
A
< +125
o
C or -40
o
C to +85
o
C; Vcc = 5V +10%)
DESCRIPTION
READ CYCLE
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold From Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Acess Time
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
WRITE CYCLE
WRITE Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
Address Hold From End of Write
WRITE Pulse Width
Data Setup Time
Data Hold Time
Write Disable to Output in Low-Z
Write Enable to Output in High-Z
SYM
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
0
0
12
12
12
0
0
12
6.5
0
0
0
6.5
6.5
2
2
0
6.5
7
0
0
15
15
15
0
0
15
7
0
0
0
7
7
-12
-15
-17
-20
-25
-35
-45
UNITS NOTES
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
12
12
12
2
2
0
7
8
0
0
17
16
16
0
0
16
9
0
0
0
8
8
15
15
15
2
2
0
8
8
0
0
20
17
17
0
0
17
10
0
0
0
8
8
17
17
17
2
2
0
8
10
0
0
25
20
20
0
0
20
12
0
0
0
10
10
20
20
20
2
2
0
10
12
0
0
35
30
30
0
0
30
20
0
0
0
15
15
25
25
25
2
2
0
15
15
0
0
45
35
35
0
0
35
25
0
0
0
20
20
35
35
35
2
2
0
20
25
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
SRAM
AS5C512K8
Rev. 7.5 01/13
Micross Components reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
AC TEST CONDITIONS
AC TEST CONDITIONS
Input pulse levels ............................................... Vss to 3.0V
to 3.0V
Input pulse levels ...................................................... Vss
Input rise and fall times .................................................. 3ns
Input rise and fall times ......................................................... 3ns
Input timing reference levels ........................................ 1.5V
Input timing reference levels ............................................... 1.5V
Output reference levels .................................................. 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1
Output load ................................................. See Figures 1 and 2
AS5C512K8
AS5C512K8
SRAM
SRAM
Q
167 ohms
C=30pF
1.73V
Q
167 ohms
C=5pF
1.73V
Fig. 1 Output Load
Fig. 1 Output Load
Equivalent
Equivalent
Fig. 2 Output Load
Fig. 2 Output Load
Equivalent
Equivalent
and 2
1.
2.
3.
4.
5.
6.
7.
NOTES
NOTES
All voltages referenced to V
SS
(GND).
1.
8. WE\ is HIGH for READ cycle.
selected. Chip enables and
9. Device is continuously
All voltages referenced to V
SS
(GND).
9. Device is continuously selected. Chip enables and
2. -2V for pulse width < 20ns
output enables are held in their active state.
-2V for pulse width < 20ns
output loading and cycle rates.
output enables are held in their active state.
with, latest
3. I
CC
is dependent on
10. Address valid prior to, or coincident
I
CC
is dependent on output loading and cycle rates.
10. Address valid prior to, or coincident with, latest
4. This parameter is guaranteed but not tested.
occurring chip enable.
This parameter is guaranteed but not tested.
output loading
occurring chip enable.
5. Test conditions as specified with the
11.
t
RC = Read Cycle Time.
Test conditions as specified with the output loading
11.
t
RC = Read Cycle Time.
write enable can initiate and
as shown in Fig. 1 unless otherwise noted.
12. Chip enable and
t
t
t
t
t
as shown in Fig. 1 unless otherwise noted.
HZOE and
t
HZWE
Chip enable and write enable can initiate and
12.
6. LZCE, LZWE, LZOE, HZCE,
terminate a WRITE cycle.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
is
terminate a WRITE cycle.
is inactive (HIGH).
are specified with CL = 5pF as in Fig. 2. Transition
13. Output enable (OE\)
are specified with CL = 5pF as in Fig. 2. Transition is
13. Output enable (OE\) is inactive (HIGH).
measured ±200mV from steady state voltage.
14. Output enable (OE\) is active (LOW).
measured ±200mV from steady state voltage.
condition,
14. Output enable (OE\) is active (LOW).
7. At any given temperature and voltage
15. ASI does not warrant functionality nor reliability of
t
t
t
At any given temperature and voltage condition,
is less than
15. ASI does not warrant functionality nor reliability of
HZCE is less than LZCE, and HZWE
any product in which the junction temperature
t
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
any product in which the junction temperature
to limit power to
LZWE.
exceeds 150°C. Care should be taken
t
LZWE.
WE\ is HIGH for READ cycle.
exceeds 150°C. Care should be taken to limit power to
8.
acceptable levels.
acceptable levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS
(L Version
Version Only)
DATA RETENTION ELECTRICAL CHARACTERISTICS
(L
Only)
DESCRIPTION
DESCRIPTION
CONDITIONS
CONDITIONS
SYM
V
DR
SYM
MIN MAX UNITS
MIN MAX UNITS NOTES
V
DR
2
I
CCDR
2
t
0
CDR
10
R
t
NOTES
CE\ > V
CE\ > V
CC
-0.2V
CC
-0.2V
Vcc for Retention Data
Vcc for Retention Data
V
-0.2 or 0.2V
V
IN
> V
CC
IN
> V
CC
-0.2 or 0.2V
Data Retention
Data Retention Current
Current
Chip Deselect to Data
to Data
Chip Deselect
Operation Recovery Time
Operation Recovery Time
2
V
V
uA
4
ns
4,
ms
11
Vcc
I
2.0V
Vcc = 2.0V
=
CCDR
t
CDR
t
R
800
mA
0
ns
4
4, 11
10
ms
AS5C512K8
AS5C512K8
Rev. 7.5 01/13
7.0 05/08
Rev.
Micross Components reserves the right to change products or specifications without notice.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5
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