White Electronic Designs
FEATURES
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WF512K32-XXX5
512Kx32 5V FLASH MODULE, SMD 5962-94612
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Organized as 512Kx32
Commercial, Industrial and Military Temperature
Ranges
5 Volt Programming. 5V ± 10% Supply.
Low Power CMOS, 6.5mA Standby
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
Built-in Decoupling Caps for Low Noise Opera
tion
Page Program Operation and Internal Program
Control Time
Weight
WF512K32 - XG2UX5 - 8 grams typical
WF512K32 - XH1X5 - 13 grams typical
WF512K32N - XG4X5
1
- 20 grams typical
WF512K32 - XG4TX5
1
- 20 grams typical
WF512K32 - XG1UX5
1
- 5 grams typical
WF512K32 - XG1TX5 - 5 grams typical
WF512K32-XG2LX5 - 8 grams typical
Access Times of 60, 70, 90, 120, 150ns
Packaging
66 pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400
(1)
).
68 lead, 40mm, Low Capacitance Hermetic
CQFP (Package 501)
1
68 lead, 40mm, Low Profile 3.5mm (0.140"),
CQFP (Package 502)
1
68 lead, 22.4mm (0.880") Low Profile CQFP
(G2U) 3.5mm (0.140") high, (Package 510)
1
68 lead, 23.9mm (0.940") Low Profile CQFP
(G1U)
1
3.5mm (0.140") high, (Package 519)
68 lead, 23.9mm (0.940") Low Profile
CQFP (G1T), 4.06mm (0.160") high,
Package (524)
68 lead, 22.4mm (0.880") CQFP (G2L)
5.08mm (0.200") high, Package (528)
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100,000 Erase/Program Cycles Minimum
Sector Architecture
8 equal size sectors of 64KBytes each
Any combination of sectors can be concur
rently erased. Also supports full chip erase
Note 1: Package Not Recommended for New Design
See Flash Programming Application Note 4M5 for algorithms.
F
IG
. 1 P
IN
C
ONFIGURATION
F
OR
WF512K32N-XH1X5
T
OP
V
IEW
I/O
0-31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
W E
1
CS
1
OE
A
0
-
18
P
IN
D
ESCRIPTION
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
B
LOCK
D
IAGRAM
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
512K x 8
512K x 8
512K x 8
512K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
August 2003 Rev. 6
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
T
OP
V
IEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GND
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
WF512K32-XXX5
F
IG
. 2 P
IN
C
ONFIGURATION
F
OR
WF512K32F-XG4X5
1
(L
OW
C
APACITANCE
) A
ND
WF512K32-XG4TX5
1
P
IN
D
ESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-18
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
WE
CS1-4
OE
VCC
GND
NC
B
LOCK
D
IAGRAM
CS
1
WE
OE
A
0-18
512K x 8
512K x 8
CS
2
CS
3
CS
4
512K x 8
512K x 8
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
A
17
A
18
NC
NC
NC
NC
NC
8
8
8
8
Note 1: Package not recommended for new designs
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
F
IG
. 3 P
IN
C
ONFIGURATION
F
OR
WF512K32-XG2UX5, WF512K32-XG2LX5, WF512K32-XG1TX5 AND
WF512K32-XG1UX5
1
T
OP
V
IEW
P
IN
D
ESCRIPTION
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
I/O0-31 Data Inputs/Outputs
A0-18
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
16
CS
1
OE
CS
2
A
17
WE
2
WE
3
WE
4
V
CC
A
11
A
12
A
13
A
14
A
15
A
18
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
NC
WE1-4
CS1-4
OE
VCC
GND
B
LOCK
D
IAGRAM
WE
1
CS
1
OE
A
0-18
512K x 8
512K x 8
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
512K x 8
512K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
2
White Electronic Designs
A
BSOLUTE
M
AXIMUM
R
ATINGS
(1)
Parameter
Operating Temperature
Supply Voltage Range (V
CC
)
Signal voltage range (any pin except A9) (2)
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Data Retention (Mil Temp)
Endurance - write/erase cycles (Mil Temp)
-55 to +125
-2.0 to +7.0
-2.0 to +7.0
-65 to +150
+300
20 years
100,000 cycles min.
Unit
°C
V
V
°C
°C
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA)
CQFP G4T
CQFP G2U/G1U/G1T/G2L
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
WF512K32-XXX5
C
APACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
50
15
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max Unit
50
pF
pF
A9 Voltage for sector protect (V
ID
) (3)
-2.0 to +14.0
V
NOTES:
1. Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels
may degrade performance and affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage
transitions,inputs may overshoot Vss to -2.0 V for periods of up
to 20ns. Maximum DC voltage on output and I/O pins is Vcc +
0.5V. During voltage transitions, outputs may overshoot to Vcc +
2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A9 pin is -0.5V. During voltage
transitions, A9 may overshoot Vss to -2V for periods of up to
20ns. Maximum DC input voltage on A9 is +13.5V which may
overshoot to 14.0 V for periods up to 20ns.
This parameter is guaranteed by design but not tested.
L
OW
C
APACITANCE
CQFP
(T
A
= +25°C)
Parameter
OE capacitance
CQFP G4 capacitance
CS1-4 capacitance
Data I/O capacitance
Address input capacitance
Symbol
COE
CWE
CCS
CI/O
CAD
Conditions
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VI/O = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
Max Unit
32
pF
32
pF
15
pF
15
pF
32
pF
R
ECOMMENDED
O
PERATING
C
ONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
A
9
Voltage for Sector Protect
Symbol
V
CC
V
IH
V
IL
T
A
T
A
V
ID
Min
4.5
2.0
-0.5
-55
-40
11.5
Max
5.5
V
CC
+ 0.5
+0.8
+125
+85
12.5
Unit
V
V
V
°C
°C
V
This parameter is guaranteed by design but not tested.
DC C
HARACTERISTICS
- CMOS C
OMPATIBLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C
TO
+125°C)
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program or Erase (2)
V
CC
Standby Current
V
CC
Static Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LOx32
I
CC1
I
CC2
I
CC4
I
CC3
V
OL
V
OH1
Conditions
V
CC
= 5.5, V
IN
= GND or V
CC
V
CC
= 5.5, V
IN
= GND or V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz
CS = V
IL
, OE = V
IH
V
CC
= 5.5, CS = V
IH
, f = 5MHz
V
CC
= 5.5, CS = V
IH
I
OL
= 8.0 mA, V
CC
= 4.5
I
OH
= 2.5 mA, V
CC
= 4.5
0.85
X
Min
Max
10
10
190
240
6.5
0.6
0.45
Unit
µA
µA
mA
mA
mA
mA
V
V
V
V
CC
Low V
CC
Lock-Out Voltage
V
LKO
3.2
4.2
DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency
component typically is less than2
mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C
TO
+125°C)
Parameter
Symbol
Min
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
tAVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
0
11
64
tWC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
60
0
40
0
40
0
40
20
300
15
0
11
64
-60
Max
-70
Min
70
0
45
0
45
0
45
20
300
15
0
11
64
Max
Min
90
0
45
0
45
0
45
20
-90
WF512K32-XXX5
AC C
HARACTERISTICS
W
RITE
/E
RASE
/P
ROGRAM
O
PERATIONS
,CS C
ONTROLLED
-120
Min
120
0
50
0
50
0
50
20
300
15
0
11
64
300
15
0
11
64
Max
-150
Min
150
0
50
0
50
0
50
20
300
15
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
sec
sec
Unit
Max
F
IG
. 4 AC T
EST
C
IRCUIT
Parameter
AC T
EST
C
ONDITIONS
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
Unit
V
ns
V
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
1.5
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75W.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
4
White Electronic Designs
WF512K32-XXX5
AC C
HARACTERISTICS
W
RITE
/E
RASE
/P
ROGRAM
O
PERATIONS
, WE C
ONTROLLED
(V
CC
= 5.0V, T
A
= -55°C
TO
+125°C)
Parameter
Symbol
Min
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time before Write
V
CC
Set-up Time
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (4)
Chip Erase Time (3)
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
4. For Toggle and Data Polling.
t
OES
t
OEH
0
10
64
t
AVAV
t
ELWL
t
WLWH
t
AVWH
t
DVWH
t
WHDX
t
WHAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
0
50
11
0
10
64
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
60
0
40
0
40
0
40
20
300
15
0
50
11
0
10
64
-60
Max
Min
70
0
45
0
45
0
45
20
300
15
0
50
11
0
10
64
-70
Max
-90
Min
90
0
45
0
45
0
45
20
300
15
0
50
11
0
10
64
Max
Min
-120
Max
-150
Min
Max
Unit
WF512K32-XXX5
120
150
ns
0
50
0
50
0
50
20
300
15
0
50
11
0
50
0
50
0
50
20
300
15
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
µs
sec
ns
ns
sec
AC C
HARACTERISTICS
R
EAD
O
NLY
O
PERATIONS
(V
CC
= 5.0V, T
A
= -55°C
TO
+125°C)
Parameter
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Address, CS or OE Change,
whichever is First
1. Guaranteed by design, but not tested
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
0
60
60
60
30
20
20
0
-60
Max
Min
70
70
70
35
20
20
0
-70
Max
Min
90
90
90
35
20
20
0
-90
Max
Min
120
120
120
50
30
30
0
-120
Max
-150
Min
150
150
150
55
35
35
Max
ns
ns
ns
ns
ns
ns
ns
Unit
5
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