HIGH SPEED
2K X 16 DUAL-PORT
SRAM
Features
◆
◆
◆
◆
◆
◆
IDT7133SA/LA
IDT7143SA/LA
◆
◆
◆
◆
High-speed access
– Military: 25/35/45/55/70/90ns (max.)
– Industrial: 25/35/55ns (max.)
– Commercial: 20/25/35/45/55/70/90ns (max.)
Low-power operation
– IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
– IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
Versatile control for write: separate write control for lower
and upper byte of each port
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
On-chip port arbitration logic (IDT7133 only)
◆
◆
◆
BUSY
output flag on IDT7133;
BUSY
input on IDT7143
Fully asynchronous operation from either port
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Description
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port
Functional Block Diagram
R/W
LUB
CE
L
R/W
RUB
CE
R
R/W
LLB
OE
L
R/W
RLB
OE
R
I/O
8L
- I/O
15L
I/O
0L
- I/O
7L
BUSY
L
(1)
A
10L
A
0L
ADDRESS
DECODER
11
I/O
CONTROL
I/O
CONTROL
I/O
8R
- I/O
15R
I/O
0R
- I/O
7R
BUSY
R
(1)
MEMORY
ARRAY
ADDRESS
DECODER
11
A
10R
A
0R
CE
L
ARBITRATION
LOGIC
(IDT7133 ONLY)
CE
R
2746 drw 01
NOTE:
1. IDT7133 (MASTER):
BUSY
is open drain output and requires pull-up resistor.
IDT7143 (SLAVE):
BUSY
is input.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC 2746/13
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
RAM or as a “MASTER” Dual-Port RAM together with the IDT7143
“SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by
CE,
permits the on-chip circuitry of each
Pin Configurations
(1,2,3)
INDEX
port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 1,150mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW for a 2V battery.
The IDT7133/7143 devices have identical pinouts. Each is packed
in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin
TQFP. Military grade product is manufactured in compliance with the
latest revision of MIL-PRF-38535 QML, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
I/O
15L
V
CC
(1)
GND
(2)
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
V
CC
(1)
R/W
LUB
R/W
LLB
OE
L
A
10L
A
9L
A
8L
A
7L
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT7133/43
J68-1 / F68-1
(4)
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
68-Pin PLCC/Flatpack
Top View
(5)
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
BUSY
L
CE
L
CE
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
,
2746 drw 02
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
(2)
R/W
RUB
R/W
RLB
OE
R
A
10R
A
9R
A
8R
A
7R
A
6R
Index
6.42
2
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
OE
R
R/W
RLB
GND
N/C
CE
R
R/W
RUB
N/C
N/C
N/C
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
NOTES:
1. Both V
CC
pins must be connected to the power supply to ensure reliable
operation.
2. Both GND pins must be connected to the ground supply to ensure reliable
operation.
3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in.
F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in.
PN100-Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
V
CC
R/W
LLB
N/C
CE
L
R/W
LUB
N/C
N/C
N/C
A
10L
A
9L
A
8L
A
7L
A
6L
IDT7133/43PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
N/C
BUSY
L
GND
N/C
BUSY
R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
2746 drw 03
,
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
51
50
48
46
44
42
40
38
36
11
53
A
6L
52
A
5L
49
A
3L
47
A
1L
45
BUSY
L
43
CE
R
41
A
0R
39
A
2R
37
A
4R
35
34
10
55
A
8L
54
A
7L
A
4L
A
2L
A
0L
CE
L
BUSY
R
A
1R
A
3R
A
5R
32
A
6R
33
09
A
10L
57
56
A
9L
A
8R
30
A
7R
31
08
R/W
LLB
59
OE
L
58
A
10R
28
A
9R
29
07
V
CC(1)
61
R/W
LUB
60
R/W
RLB
OE
R
27
IDT7133/43G
GU68-1
(4)
68-Pin PGA
Top View
(5)
26
06
I/O
1L
63
I/O
0L
62
GND
(2)
R/W
RUB
24
25
05
I/O
3L
65
I/O
2L
64
I/O
14R
22
I/O
15R
23
04
I/O
5L
67
I/O
4L
66
I/O
12R
20
I/O
13R
21
03
I/O
7L
68
1
I/O
6L
3
5
7
9
11
13
15
I/O
10R
18
I/O
11R
19
02
I/O
8L
2
I/O
9L
4
I/O
11L
6
I/O
13L
8
I/O
15L
GND
(2
)
10
I/O
1R
12
I/O
3R
14
I/O
5R
16
I/O
8R
17
I/O
9R
01
Pin 1
Designator
A
I/O
10L
B
I/O
12L
C
I/O
14L
D
V
CC(1)
E
I/O
0R
F
I/O
2R
G
I/O
4R
H
I/O
6R
J
I/O
7R
K
L
2746 drw 04
NOTES:
1. Both V
CC
pins must be connected to the power supply to ensure reliable operation.
2. Both GND pins must be connected to the ground supply to ensure reliable operation.
3. Package body is approximately 1.18 in x 1.18 in x 0.16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
CE
L
R/W
LUB
R/W
LLB
OE
L
A
0L
- A
10L
I/O
0L
- I/O
15L
BUSY
L
Right Port
CE
R
R/W
RUB
R/W
RLB
OE
R
A
0R
- A
10R
I/O
0R
- I/O
15R
BUSY
R
V
CC
GND
Chip Enable
Upper Byte Read/Write Enable
Lower Byte Read/Write Enable
Output Enable
Address
Data Input/Output
Busy Flag
Power
Ground
2746 tbl 01
Names
3
6.42
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
Maximum Operating
Temperature and Supply Voltage
(1,2)
Grade
Military
Ambient
Temperature
-55
O
C to +125
O
C
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
2746 tbl 04
T
BIAS
T
STG
P
T
(3)
I
OUT
-55 to +125
-65 to +150
2.0
50
-65 to +135
-65 to +150
2.0
50
o
C
C
Commercial
Industrial
o
W
mA
2746 tbl 02
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2746 tbl 05
Capacitance
(T
A
= +25°C, f = 1.0mhz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
11
11
Unit
pF
pF
2746 tbl 03
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(Either port, V
CC
= 5.0V ± 10%)
7133SA
7143SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage (I/O
0
-I/O
15
)
Open Drain Output Low Voltage
(BUSY)
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OL
= 16mA
I
OH
= -4mA
Min.
___
7133LA
7143LA
Min.
___
Max.
10
10
0.4
0.5
___
Max.
5
5
0.4
0.5
___
Unit
µA
µA
V
V
V
2746 tbl 06
___
___
___
___
___
___
2.4
2.4
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
6.42
4
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Operating
Temperature and Supply Voltage Range
(2)
(V
CC
= 5.0V ± 10%)
7133X20
7143X20
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
f = f
MAX
(3)
Version
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(1)
250
230
____
____
7133X25
7143X25
Com'l, Ind
& Military
Typ.
(1)
250
230
250
230
25
25
25
25
140
100
140
100
1.0
0.2
1.0
0.2
140
120
140
120
Max.
300
270
330
300
80
70
90
80
200
170
230
190
15
4
30
10
190
170
220
200
7133X35
7143X35
Com'l, Ind
& Military
Typ.
(1)
240
210
240
220
25
25
25
25
120
100
120
100
1.0
0.2
1.0
0.2
120
100
120
100
Max.
295
250
325
295
70
60
75
65
180
160
200
180
15
4
30
10
170
150
190
170
2746 tbl 07a
Max.
310
280
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(3)
25
25
____
____
80
70
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(4)
f=f
MAX
(3)
Active Port Outputs Disabled
140
120
____
____
200
180
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
1.0
0.2
____
____
15
5
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
140
120
____
____
190
170
____
____
mA
7133X45
7143X45
Com'l &
Military
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
f = f
MAX
(3)
Version
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(1)
230
210
230
210
25
25
25
25
120
100
120
100
1.0
0.2
1.0
0.2
120
100
120
100
Max.
290
250
320
290
75
65
80
70
190
170
210
190
15
4
30
10
180
160
200
180
7133X55
7143X55
Com'l, Ind
& Military
Typ.
(1)
230
210
230
210
25
25
25
25
120
100
120
100
1.0
0.2
1.0
0.2
120
100
120
100
Max.
285
250
315
285
70
60
80
70
180
160
210
190
15
4
30
10
170
150
200
180
7133X70/90
7143X70/90
Com'l &
Military
Typ.
(1)
230
210
230
210
25
25
25
25
120
100
120
100
1.0
0.2
1.0
0.2
120
100
120
100
Max.
280
250
310
280
70
60
75
65
180
160
200
180
15
4
30
10
170
150
190
170
2746 tbl 07b
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(3)
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(4)
f=f
MAX
(3)
Active Port Outputs Disabled
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
mA
NOTES:
1. V
CC
= 5V, T
A
= +25°C for Typ., and are not production tested. I
CCDC
= 180mA (typ.)
2. 'X' in part number indicates power rating (SA or LA)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ t
RC,
and using “AC Test Conditions" of input levels of
GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5
6.42
FPGA/CPLD
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