AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
EEPROM
AVAILABLE AS MILITARY
SPECIFICATIONS
•
•
SMD 5962-94614: AS8E32K32
MIL-STD-883
PIN ASSIGNMENT (Top View)
66 Lead PGA
FEATURES
•
•
•
•
•
•
Access times of 90, 120, 150 ns
Built in decoupling caps for low noise
operation
Organized as 32K x 32; User configurable
as 64K x 16 or 128K x 8
Operation with single 5 volt supply
Low power CMOS
TTL Compatible Inputs and Outputs
OPTIONS
•
Timing
90 ns
120 ns
150 ns
MARKINGS
-9
-12
-15
68 Lead CQFP
•
Package
Ceramic Quad Flatpack
Pin Grid Array
Q
P
No. 705
No. 805
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8E32K32 is a 1 Megabit
EEPROM Modules organized as 32K x 32 bit. User configurable to
64K x16 or 128Kx 8. The module achieves high speed access, low
power consumption and high reliability by employing advanced
CMOS memory technology.
The military grade product is manufactured in compliance to
the SMD and MIL-STD 883, making the AS8E32K32 ideally suited
for military or space applications.
The module is offered in a 1.090 sq inch ceramic pin grid array
substrate. This package design provides the optimum space saving
solution for boards that accept through hole packaging.
The module is also offered as a 68 lead 0.990 sq. inch ceramic
quad flatpack. It has a max. height of 0.200 inch. This package
design is targeted for those applications which require low profile
SMT Packaging.
CE4
WE4
M3
32K x 8
CE3
WE3
M2
32K x 8
I/O 24 - I/O 31
DEVICE IDENTIFICATION
An extra 64 bytes of EEPROM memory is available on each die
for user identification. By raising A9 to 12 V +/- 0.5V and using
address locations 7FC0H to 7FFFH the bytes may be written to
or read from in the same manner as the regular memory array.
CE2
WE2
M1
I/O 16 - I/O 23
32K x 8
CE1
WE1
OE
A0 - 14
M0
32K x 8
I/O 8 - I/O 23
I/O 0 - I/O 7
AS8E32K32
REV. 1.5 9/99
1
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
DEVICE OPERATION
AS8E32K32
32K x 32 EEPROM
The 32Kx 32 EEPROM memory soultion is an electricaly erasable and programmable memory module that is accessed like a
Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte-page register to
allow writing of up to 64 bytes of data simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically
write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end
of a write cycle has been detected a new access for a read or write can begin.
READ
The memory module is accessed like a Static RAM. When
CE\ and OE\ are low and WE\ is High, the data stored at the
memory location determined by the address pins is asserted on
the outputs. The module can be read as a 32 bit, 16 bit or 8 bit
device. The outputs are put in the high impedance state when
either CE\ or OE\ is high. This dual-line control gives designers
flexibility in preventing bus contention in their system.
data will be read. Reading the toggle bit may begin at any time
during the write cycle.
DATA PROTECTION
If precautions are not taken, inadvertent writes may occur
during transitions of the host power supply. The E
2
module has
incorporated both hardware and software features that will
protect the memory against inadvertent writes.
BYTE WRITE
A low pulse on the WE\ or CE\ input with CE\ or WE\ low
(respectively) and OE\ high initiates a write cycle. The address is
latched on the falling edge of CE\ or WE\, whichever occurs last.
The data is latched by the first rising edge of CE\ or WE\. Once a
BWDW (byte, word or double word) write has bee
n started it
HARDWARE PROTECTION
Hardware features protect against inadvertent writes to the
module in the following ways: (a) VCC sense - if VCC is below
3.8 V (typical) the write function is inhibited; (b) VCC power-on
delay - once VCC has reached 3.8 V the device will automatically
time out 5 ms (typical) before allowing a write; (c) write inhibit -
holding any one of OE\ low, CE\ high or WE\ high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE\ or CE\ inputs will not initiate a write cycle.
will automatically time itself to completion.
PAGE WRITE
The page write operation of the 32K x 32 EEPROM allows
1 to 64 BWDWs of data to be written into the device during a
single internal programming period. Each new BWDW must be
written within 150-µs (tBLC) of the previous BWDW. If the
tBLC limit is exceeded the device will cease accepting data and
commence the internal programming operation. For each WE
high to low transition during the page write operation, A6-A14
must be the same.
The A0-A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any order
and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been
implemented on the memory module. When enabled, the
software data protection (SDP), will prevent inadvertent writes.
The SDP feature may be enabled or disabled by the user and is
shipped with SDP disabled.
SDP is enabled by the host system issuing a series of thre e
write commands; three specific bytes of data are written to three
specific addresses (refer to Software Data Protection Algorithm).
After writing the three byte command sequence and after tWC
the entire module will be protected from inadvertent write
operations. It should be noted, that once protected the host may
still perform a byte of page write to the module. This is done by
preceding the data to be written by the same three byte command
sequence used to enable SDP.
Once set, SDP will remain active unless the disable
command sequence is issued. Power transitions do not disable
SDP and SDP will protect the 32K x 32 EEPROM module during
power-up and Power-down conditions. All command sequences
must conform to the page write timing specifications. The data
in the enable and disable command sequences is not written to the
device and the memory addresses used in the sequence may be
written with data in either a byte of page write operation.
After setting SDP, any attempt to write to the device
without the three byte command sequence will start the internal
write timers. No data will be written to the device; however, for
the duration of tWC, read operations will effectively be polling
operations.
DATA POLLING
this memory module features DATA Polling to indicate the
end of a write cycle. During a byte or page write cycle an
attempted read of the last byte written will result in the comple-
ment of the written data to be presented on I/O7. Once the write
cycle has been completed, true data is valid on all outputs, and
the next write cycle may begin. DATA Polling may begin at
anytime during the write cycle.
TOGGLE BIT
In addition to DATA Polling the module provides another
method for determining the end of a write cycle. During the write
operation, successive attempts to read data from the device will
result in I/O6 of the accessed die toggling between one and zero.
Once the write has completed, I/O6 will stop toggling and valid
AS8E32K32
REV. 1.5 9/99
2
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc ..........................................................................-.6V to +6.5V
Storage Temperature ........................................-65°C to +150°C
Short Circuit Output Current (per I/O)….........................20mA
Voltage on any Pin Relative to Vss..............-.5V to Vcc+1 mA
Junction Temperature**..................................................+150°C
Thermal Resistance junction to case (θ
JC
):
Package Type Q...........................................11.3° C/W
Package Type P..............................................2.8° C/W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above
those indicated in the operation section of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
** Maximum junction temperature depends upon package
type, cycle time, loading, ambient temperature and airflow,
and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C
≤
T
A
≤
125°C; Vcc = 5V ±10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Input Leakage Current
WE\, CE\
CONDITIONS
SYMBOL
V
IH
V
IL
MIN
2
-0.5
-10
-10
-10
2.4
MAX
V
CC
+.3
0.8
10
10
10
UNITS
V
V
µA
µA
µA
V
NOTES
1
1, 2
0V
≤
V
IN
≤
V
CC
Output(s) disabled
0V
≤
V
OUT
≤
V
CC
I
OH
= -.4 mA
I
OL
= 2.1mA
I
LI
I
LO
V
OH
V
OL
V
CC
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
1
1
1
0.45
4.5
5.5
V
V
DESCRIPTION
Power Supply
Current: Operating
Power Supply
Current: Standby
CONDITIONS
CE\
≤
V
IL
; V
CC
= MAX
f = 5 MHz
OUTPUTS OPEN
CE\
≥
V
IH
; All Other Inputs
≤V
IL
or
≥
V
IH
; V
CC
= MAX
f = 5 MHz
CE\
≥
V
CC
-0.2V; V
CC
= MAX
V
IL
≤
V
SS
+0.2V or
V
IH
≥
V
CC
-0.2V; f = 0 Hz
SYMBOL
I
CC
-90
340
MAX
-120
340
-150
340
UNITS NOTES
mA
I
SBT1
12
12
12
mA
I
SBC1
1.3
1.3
1.3
mA
AS8E32K32
REV. 1.5 9/99
3
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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