SCAS096 − FEBRUARY 1990 − REVISED APRIL 1993
74ACT11873
DUAL 4 BIT D TYPE LATCH
WITH 3-STATE OUTPUTS
•
•
•
•
•
•
•
•
Inputs Are TTL-Voltage Compatible
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic Small-
Outline Packages and Standard Plastic
300-mil DIPs
DW OR NT PACKAGE
(TOP VIEW)
1C
1Q1
1Q2
1Q3
1Q4
GND
GND
GND
GND
2Q1
2Q2
2Q3
2Q4
2C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1OC
1CLR
1D1
1D2
1D3
1D4
V
CC
V
CC
2D1
2D2
2D3
2D4
2CLR
2OC
description
These dual 4-bit registers feature 3-state outputs designed specifically for bus driving. This makes these
devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
The dual 4-bit latch is transparent D-type. When the latch enable input (1C or 2C) is high, the (Q) outputs will
follow the data (D) inputs in true form, according to the function table. When the latch enable input is taken low,
the outputs will be latched. When CLR goes low, the Q outputs go low independently of enable C. The outputs
are in a high-impedance state when OC (output control) is at a high logic level.
The 74ACT11873 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
INPUTS
OC
L
L
L
L
H
CLR
L
H
H
H
X
C
X
H
H
L
X
D
X
H
L
X
X
OUTPUT
Q
L
H
L
Qo
Z
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1993, Texas Instruments Incorporated
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DALLAS, TEXAS 75265
1
SCAS096 − FEBRUARY 1990 − REVISED APRIL 1993
74ACT11873
DUAL 4 BIT D TYPE LATCH
WITH 3-STATE OUTPUTS
logic symbol
†
28
1
27
23
22
21
20
logic diagram (positive logic)
each quad latch
1OE
1CLK
1CLR
1D1
1D2
1D3
1D4
EN
C1
R
1D
2
3
4
5
1Q1
1Q2
1Q3
1Q4
OE
CLK
CLR
R
C1
D1
1D
Q1
2OE
2CLK
2CLR
2D1
2D2
2D3
2D4
15
14
16
20
19
18
17
EN
C1
R
1D
10
11
12
13
2Q1
2Q2
2Q3
2Q4
D3
D2
R
C1
1D
Q2
R
C1
1D
Q3
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
D4
R
C1
1D
Q4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
}
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2
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DALLAS, TEXAS 75265
SCAS096 − FEBRUARY 1990 − REVISED APRIL 1993
74ACT11873
DUAL 4 BIT D TYPE LATCH
WITH 3-STATE OUTPUTS
recommended operating conditions
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
Dt/Dv
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
0
− 40
0
0
4.5
2
0.8
VCC
VCC
−24
24
10
85
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = − 50
mA
A
VOH
IOH = − 24 mA
IOH = − 75 mA†
IOL = 50
mA
A
VOL
IOL = 24 mA
IOL = 75 mA†
VO = VCC or GND
VI = VCC or GND
VI = VCC or GND,
IO = 0
TEST CONDITIONS
VCC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5V
5V
4.5
13.5
±
0.5
±
0.1
8
0.9
0.1
0.1
0.36
0.36
TA = 25°C
MIN
TYP
MAX
4.4
5.4
3.94
4.94
MIN
4.4
5.4
3.8
4.8
3.85
0.1
0.1
0.44
0.44
1.65
±
5
±
1
80
1
mA
mA
mA
mA
pF
pF
V
V
MAX
UNIT
IOZ
II
ICC
DI
CC‡
Ci
Co
One input at 3.4 V,
Other inputs at GND or VCC
VI = VCC or GND
VO = VCC or GND
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
CLR low
tw
tsu
th
Pulse duration
Setup time before C
↓
Hold time after C
↓
C high
Data high
Data low
Data high
Data low
5
5
6
3
0
0
MIN
5
5
6
3
0
0
ns
ns
ns
MAX
UNIT
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SCAS096 − FEBRUARY 1990 − REVISED APRIL 1993
74ACT11873
DUAL 4 BIT D TYPE LATCH
WITH 3-STATE OUTPUTS
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
D
C
CLR
OC
OC
TO
(OUTPUT)
Q
Q
Q
Q
Q
TA = 25°C
MIN
TYP
MAX
4.4
3
4.7
5.2
2.9
1.9
2.7
5.7
5.2
7.2
6.6
8.1
8.9
6.5
4.9
6.4
8
7.8
8.8
9.1
10
10.9
9
7.1
9.1
9.5
9.1
MIN
4.4
3
4.7
5.2
2.9
1.9
2.7
5.7
5.2
MAX
10
10.2
11.3
12.3
10
8
10.3
10.2
9.8
ns
ns
ns
ns
ns
UNIT
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per latch
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF, f = 1 MHz
TYP
40
7
UNIT
pF
4
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SCAS096 − FEBRUARY 1990 − REVISED APRIL 1993
74ACT11873
DUAL 4 BIT D TYPE LATCH
WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
2 X VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 x VCC
GND
LOAD CIRCUIT
3V
1.5 V
0V
tsu
Data
Input
1.5 V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(Low-Level
Enabling)
tPZL
Low-Level
Input
1.5 V
1.5 V
0
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
1.5 V
0
tPLZ
tw
3V
3V
1.5 V
1.5 V
0
Timing Input
(see Note B)
High-Level
Input
Input
(see Note B)
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
3V
1.5 V
1.5 V
0
tPHL
VOH
50%
50%
VOL
tPLH
VOH
50%
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
50%
VOL
Output
Waveform 1
S1 at 2 x VCC
(see Note C)
tPZH
Output
Waveform 2
S1 at GND
(see Note C)
≈
VCC
50%
tPHZ
VOH
20%
VOL
50%
80%
≈
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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