FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer
October 2006
FIN24C
µSerDes™Low-Voltage 24-Bit Bi-Directional
Serializer/Deserializer
Features
■
Low power for minimum impact on battery life
tm
General Description
The FIN24C µSerDes™ is a low-power Serializer/
Deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bi-directional operation, using half duplex for multiple
sources, it is possible to increase the signal reduction to
close to 10:1. Through the use of differential signaling,
shielding and EMI filters can also be minimized, further
reducing the cost of serialization. The differential signal-
ing is also important for providing a noise-insensitive sig-
nal that can withstand radio and electrical noise sources.
Major reduction in power consumption allows minimal
impact on battery life in ultra-portable applications. A
unique word boundary technique assures that the actual
word boundary is identified when the data is deserial-
ized. This guarantees that each word is correctly aligned
at the deserializer on a word-by-word basis through a
unique sequence of clock and data that is not repeated
except at the word boundary. A single PLL is adequate
for most applications, including bi-directional operation.
■
■
■
■
■
■
■
■
■
– Multiple power-down modes
– AC coupling with DC balance
100nA in standby mode, 5mA typical operating
conditions
Cable reduction: 25:4 or greater
Bi-directional operation 50:7 reduction or greater
Up to 24 bits in either direction
Up to 20MHz parallel interface operation
Voltage translation from 1.65V to 3.6V
Ultra-small and cost-effective packaging
High ESD protection: >7.5kV HBM
Parallel I/O power supply (V
DDP
) range between
1.65V to 3.6V
Applications
■
Micro-controller or pixel interfaces
■
Image sensors
■
Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
Ordering Information
Order Number
FIN24CGFX
FIN24CMLX
Package
Number
BGA042
MLP040
Pb-Free
Yes
Yes
Package Description
42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide
40-Terminal Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square
Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only.
µSerDes
TM
is a trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
www.fairchildsemi.com
FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer
Functional Block Diagram
CKREF
STROBE
Register
PLL
cksint
0
I
Word
Boundary
Generator
+
–
CKS0+
CKS0-
DP[m+1:24]
Serializer
Control
Serializer
+
–
DSO+/DSI-
DSO-/DSI+
oe
DP[1:m]
Register
Note:
m = 20 or 22
I/O
Control
Register
Deserializer
Deserializer cksint
Control
+
–
+
–
100Ω Gated
Termination
CKSI+
CKSI-
100Ω
Termination
CKP
WORD CK
Generator
Control Logic
S1
S2
DIRI
Power Down
Control
Freq.
Control
Direction
Control
oe
DIRO
Figure 1. Block Diagram
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
www.fairchildsemi.com
2
FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer
Terminal Description
Terminal
Name
DP[1:20]
DP[21:24]
CKREF
STROBE
CKP
DSO+ / DSI–
DSO– / DSI+
I/O Type
I/O
I or O
IN
IN
OUT
DIFF-I/O
Number of
Terminals
20
4
1
1
1
2
Description of Signals
LVCMOS Parallel I/O, direction controlled by DIRI Terminal
LVCMOS Parallel Unidirectional Inputs or Outputs Dependent on State of
S1, S2 Terminals
LVCMOS Clock Input and PLL Reference
LVCMOS Strobe Signal for Latching Data into the Serializer
LVCMOS Word Clock Output
CTL Differential Serial I/O Data Signals(1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)–: Negative signal of DSO(I) pair
CTL Differential Deserializer Input Bit Clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI–: Negative signal of CKSI pair
CTL Differential Serializer Output Bit Clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO–: Negative signal of CKSO pair
LVCMOS Mode Selection Pins used to define mode of operation for some
terminals. The control terminals, DP[21:24] can be set as 4 terminals in the
same direction or two in each direction.
LVCMOS Control Input
Used to control direction of Data Flow
LVCMOS Control Output
Inversion of DIRI
Power Supply for Parallel I/O and Translation Circuitry
Power supply for core circuitry and serial I/O
Power Supply for Analog PLL Circuitry
Use Bottom Ground Plane for Ground Signals
CKSI+, CKSI–
DIFF-IN
2
CKSO+, CKSO–
DIFF-OUT
2
S1
S2
DIRI
DIRO
V
DDP
V
DDS
V
DDA
GND
IN
IN
IN
OUT
Supply
Supply
Supply
Supply
1
1
1
1
1
1
1
0
Note:
1. The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device,
the serial connections properly align without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross.
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
www.fairchildsemi.com
3
FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer
Connection Diagrams
32
STROBE
19
DP[9]
DP[10]
DP[11]
DP[12]
V
DDP
CKP
DP[13]
DP[14]
DP[15]
DP[16]
31
CKREF
30
DIRO
29
CKSO+
28
CDSO-
27
DSO+ / DSI-
26
DSO- / DSI+
25
CKSI-
24
CKSI+
23
DIRI
22
S2
21
V
DDS
20
40
DP[8]
39
DP[7]
38
DP[6]
37
DP[5]
36
DP[4]
35
DP[3]
16
34
DP[2]
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18
Figure 2. Terminal Assignments for MLP (Top View)
1
A
B
C
D
E
F
J
2
3
4
5
6
DP[17]
DP[18]
DP[19]
DP[20]
DP[21]
DP[22]
DP[23]
DP[24]
S1
V
DDA
1
A
B
C
D
E
F
J
DP[9]
DP[11]
CKP
DP[13]
DP[15]
DP[17]
DP[19]
2
DP[7]
DP[10]
DP[12]
DP[14]
DP[16]
DP[18]
DP[20]
33
DP[1]
Pin Assignments
3
DP[5]
DP[6]
DP[8]
V
DDP
GND
DP[21]
DP[22]
4
DP[3]
DP[2]
DP[4]
GND
V
DDS
V
DDA
DP[23]
5
DP[1]
STROBE
CKSO+
CKSI+
S2
DP[24]
6
CKREF
DIRO
CKSO-
CKSI-
DIRI
S1
DSO- / DSI+ DSO+ / DSI-
(Top View)
Figure 3. Terminal Assignments for µBGA
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
www.fairchildsemi.com
4
FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer
Control Logic Circuitry
The FIN24C has four signals that are selectable as two
unidirectional inputs and two unidirectional outputs, or as
four unidirectional inputs or four unidirectional outputs.
These are often used by applications for control signals.
The mode signals S1 and S2 determine the direction of
the DP[21:24] data signals. The 00 state provides for a
power-down state where all functionality of the device is
disabled or reset. The DIRI terminal controls the direc-
tion of the device in Modes 1 and 3. When in Mode 2, the
direction is controlled by both the DIRI and STROBE sig-
nals. Table 1 provides a complete description of the vari-
ous modes of operation. For unidirectional operation, the
DIRI terminal should be hardwired to a valid logic level
and the DIRO terminal should be left floating. For bi-
directional operation, the DIRO of the master device
should be connected to the DIRI of the slave device.
When operating in a bi-directional mode, the turn-around
functionality is dependent on the mode of the device. For
Modes 1 and 3, the device asynchronously passes and
inverts the DIRI signal through the device to the DIRO
signal. Care must be taken during design to ensure that
no contention occurs between the deserializer outputs
and the other devices on this port. Optimally the periph-
eral device driving the serializer should be in a HIGH-
impedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
When the device is in Mode 2 (S2 = 1, S1 = 0), the direc-
tion of operation is dependent upon both the STROBE
signal and the DIRI signal. At power-up, the mode select
signals are both LOW and the DIRO signal is the inver-
sion of the DIRI signal. After power-up, the DIRI and
STROBE signal should initially both be HIGH. When
STROBE goes LOW the device is configured as a serial-
izer and DIRO will be forced LOW. The device remains
a serializer until the DIRI signal goes LOW. When DIRI
goes LOW, the device is re-configured as a deserializer
and the DIRO signal is asserted HIGH.
When operating the SerDes in pairs, not all operating
modes are compatible. Regardless of the mode of oper-
ation, the serializer is always sending 24 bits of data and
two word boundary bits. The deserializer is always
receiving 24 bits of data and two word boundary bits. For
some modes of operation, not all of the data bits are
valid because some pins are dedicated inputs or outputs.
A value of “0” is sent in the serial stream for all invalid
data bits.
Table 1. Control Logic Circuitry
Mode
Number
0
Inputs
S2
0
Output
DIRI
0
1
0
1
0
1
0
1
S1
0
STROBE
x
x
DIRO
1
0
1
0
1
0
1
DIRO (n-1)
Device
State
na
na
Des
Ser
Des
Ser
Des
Previous
Description
Power-Down State. The device is
powered down and disabled
regardless of all other signals.
4-Bit Unidirectional Control Mode
DP[21:24] are outputs
4-Bit Unidirectional Control Mode
DP[21:24] are inputs
STROBE and DIRI operate as an
RS-Latch to change the state of
operation.
In general, DIRI and Strobe should
not be LOW at the same time.
1
2
0
1
1
0
x
x
0
0
1
1
3
1
1
x
0
1
Des
2-Bit Unidirectional Control Mode
DP[21:22] are Inputs
DP[23:24] Outputs
2-Bit Unidirectional Control Mode
DP[21:22] are Inputs
DP[23:24] Outputs
1
1
x
1
0
Ser
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
www.fairchildsemi.com
5
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
