FIN24AC 22-Bit Bi-Directional Serializer/Deserializer
January 2007
FIN24AC
22-Bit Bi-Directional Serializer/Deserializer
Features
■
Low power for minimum impact on battery life
tm
General Description
The FIN24AC µSerDes™ is a low-power Serializer/
Deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bi-directional operation, using half duplex for multiple
sources, it is possible to increase the signal reduction to
close to 10:1. Through the use of differential signaling,
shielding and EMI filters can also be minimized, further
reducing the cost of serialization. The differential signal-
ing is also important for providing a noise-insensitive sig-
nal that can withstand radio and electrical noise sources.
Major reduction in power consumption allows minimal
impact on battery life in ultra-portable applications. A
unique word boundary technique assures that the actual
word boundary is identified when the data is deserial-
ized. This guarantees that each word is correctly aligned
at the deserializer on a word-by-word basis through a
unique sequence of clock and data that is not repeated
except at the word boundary. A single PLL is adequate
for most applications, including bi-directional operation.
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– Multiple power-down modes
– AC coupling with DC balance
100nA in standby mode, 5mA typical operating
conditions
Cable reduction: 25:4 or greater
Bi-directional operation 50:7 reduction or greater
Differential signaling:
– -90dBm EMI when using CTL in lab conditions
using a near field probe
– Minimized shielding
– Minimized EMI filter
– Minimum susceptibility to external interference
Up to 22 bits in either direction
Up to 20MHz parallel interface operation
Voltage translation from 1.65V to 3.6V
Ultra-small and cost-effective packaging
High ESD protection: >8kV HBM
Parallel I/O power supply (V
DDP
) range between
1.65V to 3.6V
Applications
■
Micro-controller or pixel interfaces
■
Image sensors
■
Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
Ordering Information
Order Number
FIN24ACGFX
FIN24ACMLX
Package
Number
BGA042
MLP040
Pb-Free
Yes
Yes
Package Description
42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide
40-Terminal Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square
Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only.
µSerDes
TM
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
FIN24AC 22-Bit Bi-Directional Serializer/Deserializer
Functional Block Diagram
CKREF
STROBE
Register
PLL
0
cksint
I
Word
Boundary
Generator
+
–
CKS0+
CKS0-
DP[21:22]
Serializer
Control
Serializer
+
–
DSO+/DSI-
DSO-/DSI+
DP[1:20]
oe
Register
Register
Deserializer
Deserializer
Control
cksint
+
–
+
–
100Ω Gated
Termination
CKSI+
CKSI-
100Ω
Termination
DP[23:24]
CKP
WORD CK
Generator
Control Logic
S1
S2
DIRI
Power Down
Control
Freq.
Control
Direction
Control
oe
DIRO
Figure 1. Block Diagram
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
2
FIN24AC 22-Bit Bi-Directional Serializer/Deserializer
Terminal Description
Terminal
Name
DP[1:20]
DP[21:22]
DP[23:24]
CKREF
STROBE
CKP
DSO+ / DSI–
DSO– / DSI+
I/O Type
I/O
I
O
IN
IN
OUT
DIFF-I/O
Number of
Terminals
20
2
2
1
1
1
2
Description of Signals
LVCMOS Parallel I/O, direction controlled by DIRI pin
LVCMOS Parallel Unidirectional Inputs
LVCMOS Unidirectional Parallel Outputs
LVCMOS Clock Input and PLL Reference
LVCMOS Strobe Signal for Latching Data into the Serializer
LVCMOS Word Clock Output
CTL Differential Serial I/O Data Signals
(1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)–: Negative signal of DSO(I) pair
CTL Differential Deserializer Input Bit Clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI–: Negative signal of CKSI pair
CTL Differential Serializer Output Bit Clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO–: Negative signal of CKSO pair
LVCMOS Mode Selection terminals used to select
Frequency Range for the RefClock, CKREF
LVCMOS Control Input
Used to control direction of Data Flow:
DIRI = “1” Serializer, DIRI = “0” Deserializer
LVCMOS Control Output
Inversion of DIRI
Power Supply for Parallel I/O and Translation Circuitry
Power Supply for Core and Serial I/O
Power Supply for Analog PLL Circuitry
Use Bottom Ground Plane for Ground Signals
CKSI+, CKSI–
DIFF-IN
2
CKSO+, CKSO–
DIFF-OUT
2
S1
S2
DIRI
IN
IN
IN
1
1
1
DIRO
V
DDP
V
DDS
V
DDA
GND
OUT
Supply
Supply
Supply
Supply
1
1
1
1
0
Note:
1. The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device,
the serial connections properly align without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross.
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
3
FIN24AC 22-Bit Bi-Directional Serializer/Deserializer
Connection Diagrams
32
STROBE
19
DP[9]
DP[10]
DP[11]
DP[12]
V
DDP
CKP
DP[13]
DP[14]
DP[15]
DP[16]
31
CKREF
30
DIRO
29
CKSO+
28
CDSO-
27
DSO+ / DSI-
26
DSO- / DSI+
25
CKSI-
24
CKSI+
23
DIRI
22
S2
21
V
DDS
40
DP[8]
39
DP[7]
38
DP[6]
37
DP[5]
36
DP[4]
35
DP[3]
16
34
DP[2]
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18
33
DP[1]
Figure 2. Terminal Assignments for MLP (Top View)
1
A
B
C
D
E
F
J
2
3
4
5
6
DP[17]
DP[18]
DP[19]
DP[20]
DP[21]
DP[22]
DP[23]
DP[24]
S1
V
DDA
Pin Assignments
1
A
B
C
D
E
F
J
DP[9]
DP[11]
CKP
DP[13]
DP[15]
DP[17]
DP[19]
2
DP[7]
DP[10]
DP[12]
DP[14]
DP[16]
DP[18]
DP[20]
3
DP[5]
DP[6]
DP[8]
V
DDP
GND
DP[21]
DP[22]
4
DP[3]
DP[2]
DP[4]
GND
V
DDS
V
DDA
DP[23]
5
DP[1]
STROBE
CKSO+
CKSI+
S2
DP[24]
6
CKREF
DIRO
CKSO-
CKSI-
DIRI
S1
20
DSO- / DSI+ DSO+ / DSI-
(Top View)
Figure 3. Terminal Assignments for µBGA
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
4
FIN24AC 22-Bit Bi-Directional Serializer/Deserializer
Control Logic Circuitry
The FIN24AC has the ability to be used as a 24-bit Seri-
alizer or a 24-bit Deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin program-
ming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serial-
izer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serial-
izer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generates the opposite
state signal on DIRO. For unidirectional operation, the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For bi-
directional operation, the DIRI of the master device is
driven by the system and the DIRO signal of the master
is used to drive the DIRI of the slave device.
Turn-Around Functionality
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken during design to ensure that no contention
occurs between the deserializer outputs and the other
devices on this port. Optimally the peripheral device driv-
ing the serializer should be in a HIGH-impedance state
prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only changes
if the device is once again turned around into a deserial-
izer and the values are overwritten.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differen-
tial input buffers are shut off, differential output buffers are
placed into a HIGH-impedance state, LVCMOS outputs
are placed into a HIGH-impedance state, LVCMOS
inputs are driven to a valid level internally, and all internal
circuitry is reset. The loss of CKREF state is also enabled
to ensure that the PLL only powers up if there is a valid
CKREF signal.
In a typical application, signals do not change states other
than between the desired frequency range and the power-
down mode. This allows for system-level power-down
functionality to be implemented via a single wire for a
SerDes pair. The S1 and S2 selection signals that have
their operating mode driven to a “logic 0” should be hard-
wired to GND. The S1 and S2 signals that have their
operating mode driven to a “logic 1” should be connected
to a system level power-down signal.
Serializer/Deserializer with Dedicated I/O
Variation
The serialization and deserialization circuitry is setup for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are ever serialized or deserialized.
Regardless of the mode of operation, the serializer is
always sending 24 bits of data and two boundary bits
and the deserializer is always receiving 24 bits of data
and two word boundary bits. Bits 23 and 24 of the serial-
izer always contain the value of zero and are discarded
by the deserializer. DP[21:22] input to the serializer is
deserialized to DP[23:24] respectively.
Table 1. Control Logic Circuitry
Mode
Number
0
1
2
3
S2
0
0
0
1
1
1
1
S1
0
1
1
0
0
1
1
DIRI
x
1
0
1
0
1
0
Power-Down Mode
Description
24-Bit Serializer, 2MHz to 5MHz CKREF
24-Bit Deserializer
24-Bit Serializer, 5MHz to 15MHz CKREF
24-Bit Deserializer
24-Bit Serializer, 10MHz to 20MHz CKREF
24-Bit Deserializer
© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
www.fairchildsemi.com
5
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