DATASHEET

X95840

Quad Digital Controlled Potentiometers (XDCP™) Low Noise/Low Power/I

2

C

Bus/256 Taps

The X95840 integrates four digitally controlled

potentiometers (XDCP) on a monolithic CMOS integrated

circuit.

The digitally controlled potentiometers are implemented with

a combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

I

2

C bus interface. Each potentiometer has an associated

volatile Wiper Register (WR) and a non-volatile Initial Value

Register (IVR), that can be directly written to and read by the

user. The contents of the WR controls the position of the

wiper. At power up the device recalls the contents of the four

DCP’s IVR to the corresponding WRs.

The DCPs can be used as three-terminal potentiometers or

as two-terminal variable resistors in a wide variety of

applications including control, parameter adjustments, and

signal processing.

FN8213

Rev 2.00

July 5, 2006

Features

• Four Potentiometers in One Package

• 256 Resistor Taps-0.4% Resolution

• I

2

C Serial Interface

- Three address pins, up to eight devices/bus

• Wiper Resistance: 70 Typical @ 3.3V

• Non-Volatile Storage of Wiper Position

• Standby Current < 5µA Max

• Power Supply: 2.7V to 5.5V

• 50k, 10k Total Resistance

• High Reliability

- Endurance: 150,000 data changes per bit per register

- Register data retention: 50 years @ T



75°C

• 20 Ld TSSOP

Ordering Information

PART NUMBER

X95840WV20I-2.7*

PART

MARKING

X95840WV G

RESISTANCE

OPTION

10k

50k

PACKAGE

20 Ld TSSOP

(Pb-free)

20 Ld TSSOP

(Pb-free)

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinouts

X95840

(20 LD TSSOP)

TOP VIEW

RH3

RL3

RW3

A2

SCL

SDA

GND

RW2

RL2

RH2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

RW0

RL0

RH0

WP

V

CC

A1

A0

RH1

RL1

RW1

X95840WV20IZ-2.7* X95840WV Z G

(Note)

X95840UV20I-2.7*

X95840UV G

X95840UV20IZ-2.7* X95840UV Z G

(Note)

*Add “T1” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

FN8213 Rev 2.00

July 5, 2006

Page 1 of 13

X95840

Block Diagram

V

CC

R

H3

R

W3

R

L3

R

H2

R

W2

R

L2

R

H1

R

W1

R

L1

R

H0

R

W0

R

L0

I

2

C

INTERFACE

SDA

SCL

POWER-UP,

INTERFACE,

CONTROL AND

StAtus LOGIC

WR3

DCP3

WR2

A2

A1

A0

NON-VOLATILE

REGISTERS

WR0

WR1

DCP2

DCP1

DCP0

WP

GND

Pin Descriptions

TSSOP PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SYMBOL

RH3

RL3

RW3

A2

SCL

SDA

GND

RW2

RL2

RH2

RW1

RL1

RH1

A0

A1

V

CC

WP

RH0

RL0

RW0

“High” terminal of DCP3

“Low” terminal of DCP3

“Wiper” terminal of DCP3

Device address for the

I

2

C

interface

I

2

C interface clock

Serial data I/O for the

I

2

C

interface

Device ground pin

“Wiper” terminal of DCP2

“Low” terminal of DCP2

“High” terminal of DCP2

“Wiper” terminal of DCP1

“Low” terminal of DCP1

“High” terminal of DCP1

Device address for the

I

2

C

interface

Device address for the

I

2

C

interface

Power supply pin

Hardware write protection pin. Active low. Prevents any “Write” operation of the

I

2

C

interface.

“High” terminal of DCP0

“Low” terminal of DCP0

“Wiper” terminal of DCP0

DESCRIPTION

FN8213 Rev 2.00

July 5, 2006

Page 2 of 13

X95840

Absolute Maximum Ratings

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C

Voltage at any Digital Interface Pin

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V

CC

+0.3

V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

CC

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C

I

W

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Recommended Operating Conditions

Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C

V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional

operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Analog Specifications

SYMBOL

R

TOTAL

Over recommended operating conditions unless otherwise stated.

TEST CONDITIONS

W, U versions respectively

-20

V

CC

= 3.3V @ 25°C

Wiper current = V

CC

/R

TOTAL

70

10/10/25

Voltage at pin from GND to V

CC

0.1

1

MIN

TYP

(Note 1)

10, 50

+20

200

MAX

UNIT

k

%



pF

µA

PARAMETER

R

H

to R

L

Resistance

R

H

to R

L

Resistance Tolerance

R

W

C

H

/C

L

/C

W

I

LkgDCP

Wiper Resistance

Potentiometer Capacitance (Note 15)

Leakage on DCP Pins (Note 15)

VOLTAGE DIVIDER MODE

(0V @ RL

i

; V

CC

@ RH

i

; measured at RW

i

, unloaded; i = 0, 1, 2, or 3)

INL (Note 6)

Integral Non-linearity

Monotonic over all tap positions

U option

W option

Full-scale Error

U option

W option

DCP to DCP Matching

Any two DCPs at same tap position, same

voltage at all RH terminals, and same voltage

at all RL terminals

DCP Register set to 80 hex

-1

-0.5

0

-7

-2

1

0.5

-1

1

0.5

7

2

0

2

LSB

(Note 2)

LSB

(Note 2)

LSB

(Note 2)

LSB

(Note 2)

LSB

(Note 2)

ppm/°C

DNL (Note 5) Differential Non-linearity

ZSerror

(Note 3)

FSerror

(Note 4)

V

MATCH

(Note 7)

Zero-scale Error

TC

V

(Note 8) Ratiometric Temperature Coefficient

±4

RESISTOR MODE

(Measurements between RW

i

and RL

i

with RH

i

not connected, or between RW

i

and RH

i

with RL

i

not connected. i = 0, 1, 2 or 3)

RINL

(Note 12)

RDNL

(Note 11)

Roffset

(Note 10)

Integral Non-linearity

Differential Non-linearity

Offset

U option

W option

R

MATCH

(Note 13)

TC

R

(Note 14)

DCP to DCP Matching

Resistance Temperature Coefficient

Any two DCPs at the same tap position with

the same terminal voltages.

DCP register set between 20 hex and FF hex

DCP register set between 20 hex and

FF hex. Monotonic over all tap positions

-1

-0.5

0

-2

±45

1

0.5

1

0.5

7

2

MI

(Note 9)

MI

(Note 9)

MI

(Note 9)

MI

(Note 9)

MI

(Note 9)

ppm/°C

FN8213 Rev 2.00

July 5, 2006

Page 3 of 13

X95840

Operating Specifications

Over the recommended operating conditions unless otherwise specified.

SYMBOL

I

CC1

I

CC2

I

SB

PARAMETER

V

CC

Supply Current

(Volatile write/read)

V

CC

Supply Current

(nonvolatile write)

V

CC

Current (standby)

TEST CONDITIONS

f

SCL

= 400kHz; SDA = Open; (for

I

2

C

,

Active, Read and Volatile Write States only)

f

SCL

= 400kHz; SDA = Open; (for

I

2

C

,

Active, Nonvolatile Write State only)

V

CC

= +5.5V,

I

2

C

Interface in Standby State

V

CC

= +3.6V,

I

2

C

Interface in Standby State

I

LkgDig

Leakage Current, at

Pins A0, A1, A2, SDA, SCL,

and WP Pins

DCP Wiper Response Time

Power-on Recall Voltage

V

CC

Ramp Rate

Power-up Delay

V

CC

above Vpor, to DCP Initial Value Register recall

completed, and

I

2

C

Interface in standby state

Voltage at pin from GND to V

CC

-10

MIN

TYP

(Note 1)

MAX

1

3

5

2

10

UNITS

mA

µA

t

DCP

(Note 15)

Vpor

VccRamp

t

D

(Note 15)

SCL falling edge of last bit of DCP Data Byte to wiper

change

Minimum V

CC

at which memory recall occurs

1.8

0.2

1

2.6

µs

V

V/ms

3

ms

EEPROM SPECS

EEPROM Endurance

EEPROM Retention

SERIAL INTERFACE SPECS

V

IL

WP, A2, A1, A0, SDA, and

SCL Input Buffer LOW

Voltage

WP, A2, A1, A0, SDA, and

SCL Input Buffer HIGH

Voltage

SDA and SCL Input Buffer

Hysteresis

-0.3

0.3*V

CC

V

Temperature



75°C

150,000

50

Cycles

Years

V

IH

0.7*V

CC

V

CC

+0.3

V

Hysteresis

(Note 15)

0.05*

V

CC

0

0.4

10

400

50

900

1300

V

pF

kHz

ns

V

OL

(Note 15) SDA outPut Buffer LOW

Voltage, Sinking 4mA

Cpin

(Note 15)

f

SCL

t

IN

(Note 15)

WP, A2, A1, A0, SDA, and

SCL Pin Capacitance

SCL frEquency

Pulse Width Suppression

Any pulse narrower than the max spec is suppressed.

Time at SDA and SCL Inputs

SCL falling edge crossing 30% of V

CC

, until SDA exits

the 30% to 70% of V

CC

window.

SDA crossing 70% of V

CC

during a STOP condition, to

SDA crossing 70% of V

CC

during the following START

condition.

Measured at the 30% of V

CC

crossing.

Measured at the 70% of V

CC

crossing.

SCL rising edge to SDA falling edge. Both crossing

70% of V

CC

.

From SDA falling edge crossing 30% of V

CC

to SCL

falling edge crossing 70% of V

CC

.

t

AA

(Note 15) SCL Falling Edge to SDA

Output Data Valid

t

BUF

(Note 15)

t

LOW

t

HIGH

t

SU:STA

t

HD:STA

Time the Bus Must be Free

Before the Start of a New

Transmission

Clock LOW Time

Clock HIGH Time

START Condition Setup

Time

START Condition Hold Time

1300

600

ns

FN8213 Rev 2.00

July 5, 2006

Page 4 of 13

X95840

Operating Specifications

Over the recommended operating conditions unless otherwise specified.

(Continued)

SYMBOL

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

PARAMETER

Input Data Setup Time

Input Data Hold Time

TEST CONDITIONS

From SDA exiting the 30% to 70% of V

CC

window, to

SCL rising edge crossing 30% of V

CC

From SCL rising edge crossing 70% of V

CC

to SDA

entering the 30% to 70% of V

CC

window.

MIN

100

0

600

0

20 +

0.1 * Cb

20 +

0.1 * Cb

10

1

250

400

TYP

(Note 1)

MAX

UNITS

ns

pF

k

STOP Condition Setup Time From SCL rising edge crossing 70% of V

CC

, to SDA

rising edge crossing 30% of V

CC

.

STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both

crossing 70% of V

CC

.

From SCL falling edge crossing 30% of V

CC

, until SDA

enters the 30% to 70% of V

CC

window.

From 30% to 70% of V

CC

From 70% to 30% of V

CC

Total on-chip and off-chip

Maximum is determined by t

R

and t

F

.

For Cb = 400pF, max is about 2~2.5k.

For Cb = 40pF, max is about 15~20k

t

DH

(Note 15) Output Data Hold Time

t

R

(Note 15)

t

F

(Note 15)

Cb (Note 15)

SDA and SCL Rise Time

SDA and SCL Fall Time

Capacitive Loading of SDA

or SCL

Rpu (Note 15) SDA and SCL Bus Pull-up

Resistor Off-chip

t

WP

Non-volatile Write Cycle

(Notes 15, 16) Time

t

SU:WPA

t

HD:WPA

A2, A1, A0, and WP Setup

Time

A2, A1, A0, and WP Hold

Time

12

Before START condition

After STOP condition

600

20

ms

ns

SDA vs SCL Timing

t

F

t

HIGH

t

LOW

t

R

SCL

t

SU:STA

SDA

(INPUT TIMING)

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STA

t

AA

SDA

(OUTPUT TIMING)

t

DH

t

BUF

FN8213 Rev 2.00

July 5, 2006

Page 5 of 13

参数名称	属性值
功能数量	4
端子数量	20
最大工作温度	85 Cel
最小工作温度	-40 Cel
额定供电电压	3.3 V
额定总电阻	10000 ohm
加工封装描述	ROHS COMPLIANT, PLASTIC, TSSOP-20
无铅	Yes
欧盟RoHS规范	Yes
状态	ACTIVE
工艺	CMOS
包装形状	RECTANGULAR
包装尺寸	SMALL OUTLINE, SHRINK PITCH
表面贴装	Yes
端子形式	GULL WING
端子间距	0.6500 mm
端子涂层	MATTE TIN
端子位置	DUAL
包装材料	PLASTIC/EPOXY
温度等级	INDUSTRIAL
转换器的类型	DIGITAL POTENTIOMETER
电阻率	LINEAR
控制接口	2-WIRE SERIAL
方位数	256
最大电阻容差	20 %
额定温度系数	45 ppm/Cel

X95840WV20I-2.7

X95840WV20I-2.7概述

X95840WV20I-2.7规格参数

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