X9523
NOT RECOMMENDED FOR NEW DESIGNS
POSSIBLE SUBSTITUTE PRODUCT
ISL22323 ISL22326
DATASHEET
FN8209
Rev 2.00
August 31, 2010
Laser Diode Control for Fiber Optic Modules Dual DCP, POR, Dual Voltage
Monitors
FEATURES
• Two Digitally Controlled Potentiometers (DCPs)
—100 Tap - 10k
—256 Tap - 100k
—Nonvolatile
—Write Protect Function
• 2-Wire Industry Standard Serial Interface
• Power-On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset
• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Pin Package
—TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9523 combines two Digitally Controlled Potenti-
ometers (DCPs), V1 / Vcc Power-on Reset (POR) cir-
cuitry, qnd two programmable voltage monitor inputs
with software and hardware indicators. All functions of
the X9523 are accessed by an industry standard 2-Wire
serial interface.
The DCPs of the X9523 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The programmable POR circuit may be
used to ensure that V1 / Vcc is stable before power is
applied to the laser diode / module. The programmable
voltage monitors may be used for monitoring various
module alarm levels.
The features of the X9523 are ideally suited to simpli-
fying the design of fiber optic modules . The integra-
tion of these functions into one package significantly
reduces board area, cost and increases reliability of
laser diode modules.
BLOCK DIAGRAM
R
H1
WIPER
COUNTER
REGISTER
R
W1
R
L1
WP
PROTECT LOGIC
7 - BIT
NONVOLATILE
MEMORY
SDA
SCL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
8
CONSTAT
REGISTER
WIPER
COUNTER
REGISTER
R
H2
R
W2
R
L2
THRESHOLD
RESET LOGIC
8 - BIT
NONVOLATILE
MEMORY
MR
V3
VTRIP
3
2
-
+
-
+
+
-
POWER-ON /
LOW VOLTAGE
RESET
GENERATION
V3RO
V2
VTRIP
2
V2RO
V1 / Vcc
VTRIP
1
V1RO
FN8209 Rev 2.00
August 31, 2010
Page 1 of 29
X9523
Ordering Information
PART
NUMBER
X9523V20I-A
X9523V20I-B
PART
MARKING
X9523VIA
X9523VIB
TEMP RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP
(Pb-free)
20 Ld TSSOP
(Pb-free)
PIN CONFIGURATION
20 Pin TSSOP
R
H2
R
W2
R
L2
V3
V3RO
MR
WP
SCL
SDA
V
SS
X9523V20IZ-A X9523VZIA
(Note)
X9523V20IZ-B X9523VZIB
(Note)
*Add "T1" suffix for tape and reel.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V1 / Vcc
V1RO
V2RO
V2
NC
NC
NC
R
H1
R
W1
R
L1
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
NOT TO SCALE
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware out-
put (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two monitor
outputs can be read out via the 2-wire serial port.
Intersil’s unique circuits allow for all internal trip volt-
ages to be individually programmed with high accuracy.
This gives the designer great flexibility in changing sys-
tem parameters, either at the time of manufacture, or in
the field.
The device features a 2-Wire interface and software pro-
tocol allowing operation on an I
2
C™ compatible serial
bus.
DETAILED DEVICE DESCRIPTION
The X9523 combines two Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/Vcc power-on reset con-
trol, V1/Vcc low voltage reset control, and two supplemen-
tary voltage monitors in one package. These functions are
suited to the control, support, and monitoring of various
system parameters in fiber optic modules. The combination
of the X9523 functionality lowers system cost, increases
reliability, and reduces board space requirements.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents.
Applying voltage to V
CC
activates the Power-on Reset cir-
cuit which allows the V1RO output to go HIGH, until the
supply the supply voltage stabilizes for a period of time
(selectable via software). The V1RO output then goes
LOW. The Low Voltage Reset circuitry allows the V1RO
output to go HIGH when V
CC
falls below the minimum V
CC
trip point. V1RO remains HIGH until V
CC
returns to proper
operating level. A Manual Reset (MR) input allows the user
to externally trigger the V1RO output (HIGH).
FN8209 Rev 2.00
August 31, 2010
Page 2 of 29
X9523
PIN ASSIGNMENT
Pin
1
2
3
4
Name
R
H2
R
w2
R
L2
V3
Function
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3
input is higher than the
V
TRIP3
threshold voltage, V3RO makes a transition to a HIGH level. Connect
V3 to V
SS
when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than
V
TRIP3
and goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO
pin requires the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset
cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time t
purst
after MR has
returned to it’s normally LOW state. The reset time can be selected using bits POR1 and POR0 in the
CONSTAT Register. The MR pin requires the use of an external “pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the device DCP Write Lock feature is active (i.e. the DCP Write Lock bit is
“1”), then no “write” (volatile or nonvolatile) operations can be performedon the wiper position of any of
the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” re-
sistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up re-
sistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2
input is greater than the
V
TRIP2
threshold voltage, V2RO makes a transition to a HIGH level. Connect
V2 to V
SS
when not used.
5
V3RO
6
MR
7
WP
8
9
10
11
12
13
17
SCL
SDA
Vss
R
L1
R
w1
R
H1
V2
18
V2RO
pin. The V2RO pin requires the use of an external “pull-up” resistor.
V
TRIP2
, and goes LOW when V2 is less than
V
TRIP2
. There is no power-up reset delay circuitry on this
V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active whenever
V1 / Vcc falls below
V
TRIP1
. V1RO becomes active on power-up and remains active for a time t
purst
after the power supply stabilizes (t
purst
can be changed by varying the POR0 and POR1 bits of the
internal control register). The V1RO pin requires the use of an external “pull-up” resistor. The V1RO
pin can be forced active (HIGH) using the manual reset (MR) input pin.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than
19
V1RO
20
14, 15,
16,
V1 / Vcc
NC
Supply Voltage.
No Connect.
FN8209 Rev 2.00
August 31, 2010
Page 3 of 29
X9523
SCL
SDA
Data Stable
Figure 1.
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Data Change
Data Stable
Valid Data Changes on the SDA Bus
Serial Stop Condition
All communications must be terminated by a STOP condi-
tion, which is a LOW to HIGH transition of SDA while SCL
is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read
sequence. A STOP condition can only be issued after the
transmitting device has released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides
the clock for both transmit and receive operations. There-
fore, the X9523 operates as a slave in all applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit-
ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL-
EDGE that it received the eight bits of data. Refer to Fig-
ure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device Iden-
tifier bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent
eight bit word.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected and
no STOP condition is generated by the master, the device
will continue to transmit data. The device will terminate fur-
ther data transmissions if an ACKNOWLEDGE is not
detected. The master must then issue a STOP condition to
place the device into a known state.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions. See Figure
1.On power-up of the X9523, the SDA pin is in the input
mode.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and SCL
lines for the START condition and does not respond to any
command until this condition has been met. See Figure 2.
SCL
SDA
Start
Figure 2.
FN8209 Rev 2.00
August 31, 2010
Stop
Valid Start and Stop Conditions
Page 4 of 29
X9523
SCL
from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
1
8
9
Start
Figure 3.
Acknowledge
Acknowledge Response From Receiver
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally selects
the DCP structures in the X9523. The CONSTAT Regis-
ter may be selected using the Internal Device Address
010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined in
the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE oper-
ation (Refer to Figure 4.)
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9523
can be split up into two main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte protocol
is used. All operations however must begin with the
Slave Address Byte being issued on the SDA pin. The
Slave address selects the part of the X9523 to be
addressed, and specifies if a Read or Write operation is
to be performed.
It should be noted that in order to perform a write operation
to a DCP, the Write Enable Latch (WEL) bit must first be
set (See “WEL: Write Enable Latch (Volatile)” on page 10.).
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte consists
of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010 in
order to select the X9523.
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either the
Non Volatile Memory of a DCP (NVM), or the CONSTAT
Register) has been correctly issued (including the final
SA7
SA6 SA5
SA4
SA3
SA2
SA1
SA0
1 0 1
DEVICE TYPE
IDENTIFIER
0
INTERNAL
DEVICE
ADDRESS
R/W
READ /
WRITE
Internal Address
(SA3 - SA1)
Internally Addressed
Device
CONSTAT Register
DCP
RESERVED
010
111
All Others
Bit SA0
0
1
Operation
WRITE
READ
Figure 4.
Slave Address Format
FN8209 Rev 2.00
August 31, 2010
Page 5 of 29
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