®
HS-303ARH
Data Sheet
December 14, 2006
FN6411.0
Radiation Hardened
CMOS Dual SPDT Analog Switch
The HS-303ARH analog switch is a monolithic device
fabricated using Intersil’s dielectrically isolated Radiation
Hardened Silicon Gate (RSG) process technology to insure
latch-up free operation. It is pinout compatible and
functionally equivalent to the HS-303RH, but offers improved
300kRAD(Si) total dose capability. This switch offers low-
resistance switching performance for analog voltages up to
the supply rails. “ON” resistance is low and stays reasonably
constant over the full range of operating voltage and current.
“ON” resistance also stays reasonably constant when
exposed to radiation, being typically 29Ω pre-rad and 34Ω
post-300kRAD(Si). Break-before-make switching is
controlled by 5V digital inputs.
Features
• QML, Per MIL-PRF-38535
• Radiation Performance
- Total Dose: 3 x 10
5
RAD(Si)
- SEE: For LET = 60MeV-mg/cm
2
at 60° Incident Angle,
<150pC Charge Transferred to the Output of an Off
Switch
• No Latch-Up, Dielectrically Isolated Device Islands
• Pinout and Functionally Compatible with Intersil
HS-303RH and HI-303 Series Analog Switches
• Analog Signal Range 15V
• Low Leakage . . . . . . . . . . . . . . . . 100nA (Max, Post-Rad)
• Low r
ON
. . . . . . . . . . . . . . . . . . . . . . 60Ω (Max, Post-Rad)
• Low Standby Supply Current . . . . . . . . . . +150μA/-100μA
(Max, Post-Rad)
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-303ARH are
contained in SMD 5962-95813. A “hot-link” is provided from
our website for downloading
Pinouts
HS1-303ARH (SBDIP), CDIP2-T14
TOP VIEW
NC
S3
1
2
3
4
5
6
7
14 V+
13 S4
12 D4
11 D2
10 S2
9 IN2
8 V-
Ordering Information
ORDERING
NUMBER
5962F9581304QCC
5962F9581304QXC
5962F9581304V9A
5962F9581304VCC
5962F9581304VXC
PART
NUMBER
HS1-303ARH-8
HS9-303ARH-8
HS0-303ARH-Q
HS1-303ARH-Q
HS9-303ARH-Q
TEMP.
RANGE
(°C)
-55 to
+125
-55 to
+125
-55 to
+125
-55 to
+125
-55 to
+125
-55 to
+125
-55 to
+125
-55 to
+125
14 LD
SBDIP
D14.3
14 LD
SBDIP
D14.3
NC
S3
D3
D1
S1
IN1
GND
D3
D1
PKG.
14 LD
SBDIP
PKG.
DWG. #
D14.3
S1
IN1
GND
14 LD K14.A
Flatpack
HS9-303ARH (FLATPACK) CDFP3-F14
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
S4
D4
D2
S2
IN2
V-
14 LD K14.A
Flatpack
HS0-303ARH/PROTO HS0-303ARH/SAMPLE
HS1-303ARH/PROTO HS1-303ARH/PROTO
HS9-303ARH/PROTO HS9-303ARH/PROTO
14 LD K14.A
Flatpack
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HS-303ARH
Functional Diagram
SBDIP TRUTH TABLE
IN
N
P
D
LOGIC
0
1
SW1 AND SW2
OFF
ON
SW3 AND SW4
ON
OFF
Die Characteristics
DIE DIMENSIONS:
2690μm x 5200μm (106 mils x 205 mils)
Thickness: 483μm
±
25.4μm (19 mils
±
1 mil)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ
±
1.0kÅ
Top Metallization:
Type: AlSiCu
Thickness: 16.0kÅ
±
2kÅ
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
196
Metallization Mask Layout
HS-303ARH
IN2
V-
V+
GND
IN1
D4
D2
S4
S2
S1
S3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
2
FN6411.0
December 14, 2006
D3
D1
FPGA/CPLD
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