®
U CT
T
ROD R ODUC
P
P
ET E
75
SOL STITUTE ER HI11
OB
B
MB
E SU R
BL
Sheet
T NU
Data
SI
PO S R SI L PA
I N TE
HI5675
March 2003
FN4711.1
8-Bit, 20MSPS, Flash A/D Converter
The HI5675 is an 8-bit, analog-to-digital converter built in an
advanced CMOS process. The low power, low differential
gain and phase, high sampling rate, and single 5V supply
make the HI5675 ideal for video and imaging applications.
The adoption of a 2-step flash architecture achieves low
power consumption (60mW) at a maximum conversion
speed of 20MSPS with only a 2.5 clock cycle data latency.
The HI5675 also features digital output enable/disable and a
built in voltage reference. The HI5675 can be configured to
use the internal reference or an external reference if higher
precision is required.
Features
• Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit
±0.3
LSB (DNL)
• Maximum Sampling Frequency . . . . . . . . . . . . . . 20MSPS
• Low Power Consumption . . . . . . . . . . . . . . . . . . . . .60mW
(Reference Current Excluded)
• Built-In Sample and Hold Circuit
• Built-In Reference Voltage Self Bias Circuit
• Three-State TTL Compatible Output
• Single +5V Power Supply
• Low Input Capacitance. . . . . . . . . . . . . . . . . . . 11pF (Typ)
• Reference Impedance . . . . . . . . . . . . . . . . . . . 300Ω (Typ)
• Low Cost
Part Number Information
PART NUMBER
HI5675JCB
TEMP.
RANGE (
o
C)
-40 to 85
PACKAGE
24 Ld SOIC
PKG. NO.
M24.2-S
• Direct Replacement for TLC5510 and ADC1175
Applications
Pinout
HI5675 (SOIC)
TOP VIEW
OE
DV
SS
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
DV
DD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
24 DV
SS
23 V
RB
22 V
RBS
21 AV
SS
20 AV
SS
19 V
IN
18 AV
DD
17 V
RT
16 V
RTS
15 AV
DD
14 AV
DD
13 DV
DD
• Video Digitizing
• PC Video Capture
• Image Scanners
• TV Set Top Boxes
• Multimedia
• Personal Communication Systems (PCS)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5675
Functional Block Diagram
OE
DV
SS
D0 (LSB)
D1
D2
D3
D4
D5
D6
1
2
3
4
5
6
7
8
9
UPPER
DATA
LATCHES
LOWER
DATA
LATCHES
LOWER
ENCODER
(4-BIT)
LOWER
COMPARATORS
WITH S/H (4-BIT)
REFERENCE VOLTAGE
24 DV
SS
23 V
RB
22
V
RBS
0.6V (Typ)
21 AV
SS
20 AV
SS
LOWER
ENCODER
(4-BIT)
LOWER
COMPARATORS
WITH S/H (4-BIT)
19 V
IN
18 AV
DD
17 V
RT
D7 (MSB) 10
DV
DD
11
CLK 12
CLOCK GENERATOR
UPPER
ENCODER
(4-BIT)
UPPER
COMPARATORS
WITH S/H (4-BIT)
16
V
RTS
2.6V (Typ)
15 AV
DD
14 AV
DD
13 DV
DD
Typical Application Schematic
HC04
CA158A
R4
+
+5V
C9 +
4.7µF
C10
0.1µF
R5
+
13
14
15
CA158A
C12
0.1µF
HA2544
V
IN
+
C8
16
17
18
12
11
10
9
8
7
HI5675
19
20
R1
R2
21
22
23
C11
0.1µF
C7
4.7µF
+
24
6
5
4
3
2
1
D3
D2
D1
D0 (LSB)
D7 (MSB)
D6
D5
D4
CLOCK IN
CLK
+5V
-
R11
R3
R13
ICL8069
R12
-
†
-
+5V
†
: Ceramic Chip Capacitor 0.1µF
: Analog GND
: Digital GND
NOTE: It is necessary that AV
DD
and DV
DD
pins be driven from the same supply. The gain of analog input signal can be changed by adjusting the
ratio of R2 to R1.
2
HI5675
Pin Descriptions
PIN
NUMBER
1
2, 24
3-10
11, 13
12
16
17
23
14, 15, 18
19
20, 21
22
SYMBOL
OE
DV
SS
D0 to D7
DV
DD
CLK
V
RTS
V
RT
V
RB
AV
DD
V
IN
AV
SS
V
RBS
DESCRIPTION
When OE = Low, Data is valid. When OE = High, D0 to D7 pins high impedance.
Digital GND.
D0 (LSB) to D7 (MSB) Output.
Digital +5V. (Connect to AV
DD
to avoid Latchup).
Clock Input.
Shorted with V
RT
generates, +2.6V.
Reference Voltage (Top).
Reference Voltage (Bottom).
Analog +5V. Digital +5V. (Connect to DV
DD
to avoid Latchup).
Analog Input.
Analog GND.
Shorted with V
RB
generates +0.6V.
3
HI5675
Absolute Maximum Ratings
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Reference Voltage, V
RT
, V
RB
. . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
Analog Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
Digital Input Voltage, CLK . . . . . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
Digital Output Voltage, V
OH
, V
OL
. . . . . . . . . . . . . . . . . V
DD
to V
SS
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range, T
STG
. . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
(Note 1)
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Supply Voltage
AV
DD
, AV
SS
, DV
DD
, DV
SS
. . . . . . . . . . . . . . . . +4.75V to +5.25V
| DGND-AGND |. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV
Reference Input Voltage
V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above
V
RT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below
Analog Input Range, V
IN
. . . . . . . V
RB
to V
RT
(1.8V
P-P
to 2.8V
P-P
)
Clock Pulse Width
t
PW1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
t
PW0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
Die Characteristics
Die Size: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.23 x 2.24mm
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Offset Voltage
E
OT
E
OB
Integral Non-Linearity, INL
Differential Non-Linearity, DNL
DYNAMIC CHARACTERISTICS
Effective Number of Bits, ENOB
Spurious Free Dynamic Range
Signal to Noise Ratio, SINAD
RMS Signal
= -----------------------------------------------------------------
-
RMS Noise
+
Distortion
Maximum Conversion Speed, f
C
Minimum Conversion Speed
Differential Gain Error, DG
Differential Phase Error, DP
Aperture Jitter, t
AJ
Sampling Delay, t
DS
Data Latency, t
LAT
ANALOG INPUTS
f
C
= 20MSPS, AV
DD
= DV
DD
= 5V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C (Note 1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-60
0
f
C
= 20MSPS, V
IN
= 0.6V to 2.6V
f
C
= 20MSPS, V
IN
= 0.6V to 2.6V
-
-
-35
+15
±0.5
±0.3
-10
+45
±1.3
±0.5
mV
mV
LSB
LSB
f
IN
= 1MHz
f
IN
= 1MHz
f
C
= 20MHz, f
IN
= 1MHz
f
C
= 20MHz, f
IN
= 3.58MHz
-
-
-
-
7.6
51
46
46
-
-
-
-
Bits
dB
dB
dB
V
IN
= 0.6V to 2.6V, f
IN
= 1kHz Ramp
20
-
-
-
1.0
0.5
30
4
-
-
0.5
-
-
-
-
2.5
MSPS
MSPS
%
Degree
ps
ns
Cycles
NTSC 40 IRE Mod Ramp, f
C
= 14.3MSPS
-
-
-
-
-
Analog Input Bandwidth (-1dB), BW
Analog Input Capacitance, C
IN
V
IN
= 1.5V + 0.07V
RMS
-
-
18
11
-
-
MHz
pF
4
HI5675
Electrical Specifications
PARAMETER
REFERENCE INPUT
Reference Pin Current, I
REF
Reference Resistance (V
RT
to V
RB
), R
REF
INTERNAL VOLTAGE REFERENCE
Self Bias Mode 1
V
RB
V
RT
- V
RB
Self Bias Mode 2, V
RT
DIGITAL INPUTS
Digital Input Voltage
V
IH
V
IL
Digital Input Current
I
IH
I
IL
DIGITAL OUTPUTS
Digital Output Current
I
OH
I
OL
Digital Output Current
I
OZH
I
OZL
TIMING CHARACTERISTICS
Output Data Delay, t
DL
POWER SUPPLY CHARACTERISTIC
Supply Current, I
DD
NOTE:
2. Electrical specifications guaranteed only under the stated operating conditions.
f
C
= 20MSPS, NTSC Ramp Wave Input
-
12
17
mA
-
18
30
ns
OE = V
DD
, V
DD
= Max
V
OH
= V
DD
V
OL
= 0V
-
-
0.01
0.01
16
16
µA
µA
OE = V
SS
, V
DD
= Min
V
OH
= V
DD
-0.5V
V
OL
= 0.4V
-1.1
3.7
-
-
-
-
mA
mA
V
DD
= Max
V
IH
= V
DD
V
IL
= 0V
-
-
-
-
5
5
µA
µA
4.0
-
-
-
-
1.0
V
V
V
RB
= AGND, Short V
RT
and V
RTS
Short V
RB
and V
RBS
, Short V
RT
and V
RTS
0.60
1.96
2.25
0.64
2.09
2.39
0.68
2.21
2.53
V
V
V
4.5
230
6.6
300
8.7
450
mA
Ω
f
C
= 20MSPS, AV
DD
= DV
DD
= 5V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C (Note 1)
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Timing Diagrams
t
PW1
t
PW0
CLOCK
ANALOG INPUT
N
N+1
N-2
N-1
N+3
N
N+4
N+1
DATA OUTPUT
N-3
N-2
: POINT FOR ANALOG SIGNAL SAMPLING
t
D
= 18ns
FIGURE 1.
5
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