CommLink
TM
Direct Digital Synthesizer
IGNS
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®
NE W
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F O R PR O D U
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REC
Sheet
E S SL531 port Cen /tsc
Data
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8
1-88
HSP45314
January 2001
File Number
4820.3
Features
• 125MSPS Output Sample Rate with 5V Digital Supply
• 100MSPS Output Sample Rate with 3.3V Digital Supply
• 14-bit DAC with Internal Reference
• Parallel Control Interface for Fast Tuning (50MSPS
Control Register Write Rate)
• 48-bit Programmable Frequency Control
• Small 48-pin LQFP package
The 14-bit HSP45314 provides a complete Direct Digital
Synthesizer (DDS) system in a single 48-pin LQFP package.
A 48-bit Programmable Carrier NCO (numerically controlled
oscillator) and a high speed 14-bit DAC (digital to analog
converter) are integrated into a stand alone DDS.
The DDS accepts 48-bit center and offset frequency control
information via a parallel processor interface. Modulation
control is provided by 3 external pins. The PH0 and PH1
pins select phase offsets of 0, 90, 180 and 270 degrees,
while the ENOFR pin enables or zeros the offset frequency
word to the phase accumulator.
The parallel processor interface has an 8-bit write-only data
input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe
(WR), and a Write Enable (WE). The processor can update
all registers simultaneously by loading a set of master
registers, then transfer all master registers to the slave
registers by asserting the UPDATE pin.
Applications
• Programmable Local Oscillator
• FSK Modulation
• Direct Digital Synthesis
• Clock Generation
Block Diagram
Ordering Information
PART
NUMBER
HSP45314VI
TEMP. RANGE
(
o
C)
-40 to 85
PACKAGE
48 LQFP
PKG. NO.
Q48.7X7A
COMPOUT
C(7:0)
A(3:0)
WR
WE
UPDATE
Pinout
C3
C4
C5
C6
C7
DVDD
WR
DGND
WE
NC
A0
A1
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
34
3
33
4
32
5
31
6
HSP45314
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
1
-
+
IN-
IN+
COMP1
COMP2
MASTER
SLAVE
PHASE
ACCUM.
48-PIN LQFP (Q48.7X7A
TOP VIEW
∑
MODULATION
CONTROL
SINE
WAVE
ROM
ENOFR
PH(1:0)
14 BIT
DAC
INT
REF
IOUTA
IOUTB
REFIO
REFLO
RESET
CLK
C2
C1
C0
ENOFR
DGND
CLK
DVDD
RESET
UPDATE
COMPOUT
REFLO
REFIO
A2
A3
PH0
PH1
DGND
DVDD
DGND
DGND
DGND
DGND
DVDD
DGND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2002. All Rights Reserved
CommLink™ is a trademark of Intersil Corporation.
FSADJ
COMP1
AGND
AGND
IOUTB
IOUTA
COMP2
AVDD
AGND
IN+
IN-
AGND
HSP45314
Typical Application Circuit (Sinewave Generation)
WRITE CLOCK
WRITE ENABLE
PH1:PH0 BUS
A3:A0 BUS
C7:C0 BUS
µ
PROCESSOR/
FPGA/CPLD
CLOCK
SOURCE
DV
PP
0.1µF
FSADJ
COMP1
AGND
AGND
IOUTB
IOUTA
COMP2
AVDD
AGND
IN+
IN-
AGND
0.1µF
0.1µF
R
SET
2kΩ
AV
PP
0.1µF
0.1µF
AV
PP
50Ω 50Ω
(IOUTA) ANALOG OUTPUT
FERRITE
BEAD
+
+5V POWER SOURCE
10µF
DV
PP
(DIGITAL POWER PLANE)
10µH
FERRITE
BEAD
+
10µF
AV
PP
(ANALOG POWER PLANE)
10µH
0.1µF
1µF
0.1µF
1µF
2
SIGNAL
PROCESSING
0.1µF
C2
C1
C0
ENOFR
DGND
CLK
DVDD
RESET
UPDATE
COMPOUT
REFLO
REFIO
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
34
3
33
4
32
5
31
6
HSP45314
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
1
C3
C4
C5
C6
C7
DVDD
WR
DGND
WE
NC
A0
A1
A2
A3
PH0
PH1
DGND
DVDD
DGND
DGND
DGND
DGND
DVDD
DGND
DV
PP
DV
PP
3
0.1µF
HSP45314
Functional Description
The HSP45314 is an NCO with an integrated 14-bit DAC
designed to run in excess of 125MSPS. The NCO is a 16-bit
output design, which is rounded to 14 bits for input to the
DAC. The frequency control is the sum of a 48-bit center
frequency word and a 48-bit offset frequency word. The two
components are added modulo 48 bits with the alignment
shown in Table 1. Each of the two terms can be zeroed
independently (via the microprocessor interface for the
center frequency and via the ENOFR pin for the offset
frequency term).
Parallel Interface
The processor interface is an 8-bit parallel write only
interface. The interface consists of 8 data bits (C7:C0), four
address pins (A3:A0), a Write Strobe (WR), and a Write
Enable (WE). The interface is a master/slave type. The
processor interface loads a set of master registers. The
contents of the master set of registers is then transferred to
a slave set of registers by asserting a pin (UPDATE). This
allows all of the bits of the frequency control to be updated
simultaneously.
The rate which the user writes (WR) to these registers does
not have to be the same rate as the DDS clock rate (the rate
of the NCO and DAC; pin CLK). It is expected that most
applications will have a slower register write rate than the
DDS clock rate. It takes 6 WR cycles at the write rate plus
another 11 CLK cycles at the DDS rate to write and obtain a
new frequency, assuming that all registers are rewritten and
the UPDATE pin is always active. If the UPDATE pin is not
active until after the new word has been written, it takes 14
CLK cycles, rather than 11. For cases which require the
output to be updated with all of the new frequency
information present, it is necessary that the UPDATE be
inactive until after all of the new frequency word has been
written to the device. See the Timing Diagrams for more
information. The parallel registers can be written to again
immediately after the 11th or 14th CLK cycle, again
depending the state of UPDATE. If the application does not
need 48 bits (all 6 registers) of frequency information, then
the output frequency can be changed more quickly. For
example, if only 32 bits of frequency information are needed
and it is desired that the output be updated all at once, then
it takes 4 WR cycles, then the assertion low of the UPDATE
pin, plus another 14 CLK cycles at the DDS rate to write and
update a new frequency.
The timing is the same whether writing to the center or offset
frequency registers. For faster frequency update, consider
the ENOFR (Enable Offset Frequency Register) option.
Once the values have been written to the center and offset
frequency registers, the user can enable and disable the
offset frequency register, which is added to the center
frequency value when enabled. The ENOFR pin has a
latency of 14 CLK cycles, but simplifies the interface
because the only pin that has to be toggled is the ENOFR
pin.
Frequency Generation
The output frequency of the part is determined by the
summation of two registers:
f
OUT
= f
CLK
x ( (CF + OF) mod (2
48
))/ (2
48
),
where CF is the Center Frequency register and OF is the
Offset Frequency register.
With a 125MSPS clock rate, the center frequency can be
programmed to
(125 x 10
6
)/(2
48
) = 0.4
µ
Hz resolution.
The addition of the frequency control words can be
interpreted as two’s complement if convenient. For example,
if the center frequency is set to 4000...00h and the offset
frequency set to C000..00h, the programmed center
frequency would be f
CLK
/4 and the programmed offset
frequency -f
CLK
/4. The sum would be 10000..00h, but
because only the lower 48 bits are retained, the effective
frequency would be 0. In reality, frequencies above
8000...00h alias below f
CLK
/2 (the output of the part is real),
so the MSB is only provided as a convenience for two’s
complement calculations.
The frequency control of the NCO is the change in phase per
clock period or dφ/dt. This is integrated by the phase
accumulator to obtain frequency. The most significant 24
bits of phase are then mapped to 16 bits of amplitude in a
sine look-up table function. The range of dφ/dt is 0 to 1 with
1 equaling 360 degrees or (2 x pi) per clock period. The
phase accumulator output is also 0 to 1 with 1 equaling 360
degrees. The operations are modulo 48 bits because the
MSB (bit 47) aligns with the most significant address bit of
the sine ROM and the ROM contains one cycle of a
sinusoid. The MSB is weighted at 180 degrees. Full scale is
360 degrees minus 1 LSB and the phase then rolls over to 0
degrees for the next cycle of the sinusoid.
TABLE 1. FREQUENCY CONTROL BIT ALIGNMENTS
Bits
Individual Bit Alignment
Phase Accumulator
Center Frequency
Offset Frequency
4444 4444
7654 3210
xxxx xxxx
xxxx xxxx
xxxx xxxx
3333 3333
9876 5432
xxxx xxxx
xxxx xxxx
xxxx xxxx
3322 2222
1098 7654
xxxx xxxx
xxxx xxxx
xxxx xxxx
2222 1111
3210 9876
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1100
5432 1098
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
7654 3210
xxxx xxxx
xxxx xxxx
xxxx xxxx
3
HSP45314
Control Pins
There are three control pins provided for phase and
frequency control. The PH0 and PH1 pins select phase
offsets of 0, 90, 180, and 270 degrees and can be used for
low speed, unfiltered BPSK or QPSK modulation. These
pins can also be used for providing sine/cosine when using
two HSP45314s together as quadrature local oscillators.
The ENOFR pin enables or zeros the offset frequency word
to the phase accumulator and can be used for FSK or MSK
modulation. These control pins and the UPDATE pin are
passed through special cells to minimize the probability of
meta-stability.
V
FSADJ
will equal the external reference. The calculation for
I
OUT
(Full Scale) is:
I
OUT
(Full Scale) = (V
FSADJ
/R
SET)
X 32.
Analog Output
IOUTA and IOUTB are complementary current outputs. They
are generated by a 14-bit digital-to-analog converter (DAC)
that is capable of running at the full 125MSPS rate. The DDS
clock also clocks the DAC. The sum of the two output
currents is always equal to the full scale output current
minus one LSB. If single ended use is desired, a load
resistor can be used to convert the output current to a
voltage. It is recommended that the unused output be either
grounded or equally terminated. The voltage developed at
the output must not violate the output voltage compliance
range of -1.0V to 1.25V. R
LOAD
(the impedance loading
each current output) should be chosen so that the desired
output voltage is produced in conjunction with the output full
scale current. If a known line impedance is to be driven, then
the output load resistor should be chosen to match this
impedance. The output voltage equation is:
V
OUT
= I
OUT
X R
LOAD
.
These outputs can be used in a differential-to-single-ended
arrangement. This is typically done to achieve better
harmonic rejection. Because of a mismatch in IOUTA and
IOUTB, the transformer does not improve the harmonic
rejection. However, it can provide voltage gain without
adding distortion. The SFDR measurements in this data
sheet were performed with a 1:1 transformer on the output of
the DDS (see Figure 1). With the center tap grounded, the
output swing of pins 17 and 18 will be biased at zero volts.
The loading as shown in Figure 1 will result in a 500mV
P-P
signal at the output of the transformer if the full scale output
current of the DAC is set to 20mA.
R
EQ
IS THE IMPEDANCE
LOADING EACH OUTPUT
50Ω
PIN 17
PIN 18
HSP45314
IOUTB
100Ω
IOUTA
50Ω
50Ω REPRESENTS THE
SPECTRUM ANALYZER
V
OUT
= (2 x I
OUT
x R
EQ
)V
PP
50Ω
Reset
A RESET pin is available which resets all registers to their
defaults. In order to reset the part, the user must take the
RESET pin low, allow at least one CLK rising edge, and then
take the RESET pin high again. The latency from the RESET
pin going high until the output reflects the reset is 11 CLK
cycles. See the register description table in the back of the
datasheet for the default states of all bits in all addresses.
After RESET goes high, one rising edge of CLK is required
before the control registers can be written to again.
Comparator
A comparator is provided for square wave output generation.
The user can take the DDS analog output, filter it, and then
send it back into the comparator. A square wave will be
generated at the comparator output (COMPOUT pin) at an
amplitude level that is dependent on the digital power supply
used (DV
DD
). The comparator was designed to operate at
speeds comparable to the DDS output frequency range
(approximately 0-50MHz). It is not intended for low jitter
applications. The comparator has a sleep mode that is
activated by connecting both inputs (IN- and IN+) to the
analog power supply plane. This will save approximately
4mA of current (as shown in the Typical Application Circuit).
If the comparator is not used, leave the COMPOUT pin
floating.
DAC Voltage Reference
The internal voltage reference for the DAC has a nominal
value of +1.2V with a
±60ppm/
o
C drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(11) selects the reference. The internal reference can be
selected if pin 11 is tied low (ground). If an external reference
is desired, then pin 11 should be tied high (the analog supply
voltage) and the external reference driven into REFIO, pin
12. The full scale output current of the converter is a function
of the voltage reference used and the value of R
SET
. I
OUT
should be within the 2mA to 20mA range, though operation
below 2mA is possible, with performance degradation.
If the internal reference is used, V
FSADJ
will equal
approximately 1.2V (pin 13). If an external reference is used,
FIGURE 1.
V
OUT
= 2 x I
OUT
x R
EQ
, where R
EQ
is ~12.5Ω. Allowing the
center tap to float will result in identical transformer output,
however the output pins of the DAC will have positive DC
offset, which could limit the voltage swing available due to
the output voltage compliance range. The 50Ω load on the
output of the transformer represents the load at the end of a
‘transmission line’, typically a spectrum analyzer,
oscilloscope, or the next function in the signal chain. The
4
SIGNAL
PROCESSING
3
HSP45314
necessity to have a 50Ω impedance looking back into the
transformer is negated if the DDS is only driving a short
trace. The output voltage compliance range does limit the
impedance that is loading the DDS output.
Improving SFDR
As was previously noted, using +5V power supplies provides
the best SFDR. Under some clock and output frequency
combinations, particularly when the f
CLK
/f
OUT
ratio is less
than 4, the user can improve SFDR even further by
connecting the COMP2 pin (19) of the DDS to the analog
power supply. The digital supply must be +5V if this option is
explored. Improvements as much as 6dBc in the SFDR-to-
Nyquist measurement were seen in the lab.
Ground Plane Considerations
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane. Pins 11 through 24 are analog pins,
while all of the others are digital.
FSK Modulation
BFSK (Binary Frequency Shift Keying) can be done by
enabling and disabling the offset frequency (ENOFR pin).
Once the offset frequency has been written once, it can be
toggled with a latency of 14 CLK cycles.
M-ary FSK or GFSK can be done by continuously loading in
new frequency words.
Noise Reduction Considerations
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the power supply pins, AV
DD
and DV
DD
. Also, the layout should be designed using
separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DV
DD
and to the analog ground for AV
DD
. Additional filtering
of the power supplies on the board is recommended.
Quadrature Local Oscillators
Two HSP45314s can be used as sine/cosine generators for
quadrature local oscillator applications. It is important to note
that the Phase Accumulator feedback needs to be zeroed in
both devices if it is desired that both DDSs restart with a
known phase, which is determined by the use of the phase
control pins, PH1 and PH0. To zero the phase accumulator,
pull bit 5 of address 13 low and then high again at the same
time in both devices.
Power Supplies
The DDS will provide the best SFDR (Spurious Free
Dynamic Range) when using +5V analog and +5V digital
power supply. The analog supply must be +5V (±10%). The
digital supply can be either a +3.3V (±10%) or a +5V (±10%)
supply, or anything in between. The DDS is rated to
125MSPS when using a +5V digital supply. The maximum
clock is 100MSPS when using a +3.3V digital supply.
5
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