HIP6503
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN4882
Rev 5.00
July 21, 2005
Multiple Linear Power Controller with ACPI Control Interface
The HIP6503 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20 pin SOIC package. One linear controller
generates the 3.3V
DUAL
/3.3V
SB
voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. A linear controllers/regulator
supplies at choice either of 2.5V or 3.3V memory power
through external pass transistors (switch for 3.3V setting) in
active states. During sleep states, integrated pass
transistors supply the sleep power. Another controller
powers up the 5V
DUAL
plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
Two internal regulators output both a dedicated, noise-free
2.5V clock chip supply, as well as a 1.8V ICH2 resume well
voltage. The HIP6503’s operating mode (active outputs or
sleep outputs) is selectable through two digital control pins,
S3 and S5. Enabling sleep state support on the 5V
DUAL
output is offered through the EN5VDL pin. In active state, the
3.3V
DUAL
/3.3V
SB
and 2.5V
MEM
/3.3V
MEM
linear regulators
use external N-channel pass MOSFETs to connect the
outputs directly to the 3.3V input supplied by an ATX power
supply, for minimal losses. In sleep state, power delivery on
both outputs is transferred to NPN transistors. Active state
regulation on the 2.5V
MEM
output is performed through an
external NPN transistor. The 5V
DUAL
output is powered
through two external MOS transistors. In sleep states, a
PMOS (or PNP) transistor conducts the current from the ATX
5VSB output; while in active state, current flow is transferred
to an NMOS transistor connected to the ATX 5V output. The
operation of the 5V
DUAL
output is dictated not only by the
status of the S3 and S5 pins, but that of the EN5VDL pin as
well. The 3.3V
DUAL
/3.3V
SB
and 1.8V
SB
outputs are active
for as long as the ATX 5VSB voltage is applied to the chip.
The 2.5V
CLK
output is only active during S0 and S1/S2, and
uses the 3V3 pin as input source for its internal pass
element.
Features
• Provides 5 ACPI-Controlled Voltages
- 5V
DUAL
USB/Keyboard/Mouse
- 3.3V
DUAL
/3.3V
SB
PCI/Auxiliary/LAN
- 2.5V
MEM
RDRAM or 3.3V
MEM
SDRAM
- 2.5V
CLK
Clock/Processor Terminations
- 1.8V
SB
ICH2 Resume Well
• Excellent Output Voltage Regulation
- All Outputs:
2.0%
Over Temperature (as applicable)
• Small Size; Very Low External Component Count
• RDRAM/SDRAM/DDRAM Memory Support
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• ACPI-Compliant Power Regulation for Motherboards
Ordering Information
PART NUMBER
HIP6503CB
HIP6503CBZ (Note)
TEMP.
RANGE (°C)
0 to 70
0 to 70
PACKAGE
20 Ld SOIC
PKG.
DWG. #
M20.3
20 Ld SOIC (Pb-free) M20.3
M20.3
HIP6503CBZ-T (Note) 20 Ld SOIC Tape and Reel
(Pb-free)
HIP6503EVAL1
Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
HIP6503
(SOIC)
TOP VIEW
5VSB
1
20 VSEN2
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11
GND
1V8IN 2
1V8SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL
S3
8
9
S5 10
FN4882 Rev 5.00
July 21, 2005
Page 1 of 14
HIP6503
Absolute Maximum Ratings
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2 . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
12V
+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(°C/W)
Recommended Operating Conditions
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, V
SX
, V
EN5VDL
. . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
SOIC Package (Note 1) . . . . . . . . . . . . . . . . . . . . . .
60
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
Shutdown Supply Current
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
5VSB
I
5VSB(OFF)
V
SS
= 0.8V
-
-
30
14
-
-
mA
mA
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
Rising 5VSB POR Threshold
5VSB POR Hysteresis
Rising 12V Threshold
12V Hysteresis
Rising 3V3 and 5V Thresholds
3V3 and 5V Hysteresis
Falling Threshold Timeout (All Monitors)
Soft-Start Current
Shutdown Voltage Threshold
1.8V
SB
LINEAR REGULATOR (V
OUT1
)
Regulation
1V8SB Nominal Voltage Level
1V8SB Undervoltage Rising Threshold
1V8SB Undervoltage Hysteresis
1V8SB Output Current
2.5/3.3V
MEM
LINEAR REGULATOR (V
OUT2
)
Regulation (Note 2)
VSEN2 Nominal Voltage Level
VSEN2 Nominal Voltage Level
VSEN2 Undervoltage Rising Threshold
VSEN2 Undervoltage Hysteresis (Note 3)
VSEN2 Output Current
I
VSEN2
5VSB = 5V
V
VSEN2
V
VSEN2
R
SEL
= 1k
R
SEL
= 10k
-
-
-
-
-
250
-
2.5
3.3
83
3
300
2.0
-
-
-
-
-
%
V
V
%
%
mA
I
1V8SB
1V8IN = 3.3V
V
1V8SB
-
-
-
-
250
-
1.8
1.494
54
300
2.0
-
-
-
-
%
V
V
mV
mA
I
SS
V
SD
-
-
-
-
-
-
-
-
-
-
1.0
-
1.0
90
5
10
10
-
4.5
-
10.8
-
-
-
-
-
0.8
V
V
V
V
%
%
s
A
V
FN4882 Rev 5.00
July 21, 2005
Page 4 of 14
HIP6503
Electrical Specifications
PARAMETER
DRV2 Output Drive Current
DRV2 Output Impedance
3.3V
DUAL
/3.3V
SB
LINEAR REGULATOR (V
OUT3
)
Sleep State Regulation
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
3V3DL Undervoltage Hysteresis
3V3DLSB Output Drive Current
DLA Output Impedance
2.5V
CLK
LINEAR REGULATOR (V
OUT4
)
Regulation
VCLK Nominal Voltage Level
VCLK Undervoltage Rising Threshold
VCLK Undervoltage Hysteresis
VCLK Output Current (Note 4)
5V
DUAL
SWITCH CONTROLLER (V
OUT5
)
5VDL Undervoltage Rising Threshold
5VDL Undervoltage Hysteresis
5VDLSB Output Drive Current
5VDLSB Pull-Up Impedance to 5VSB
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 5)
Active-to-Sleep Control Input Delay
CONTROL I/O (S3, S5, EN5VDL, FAULT/MSEL)
High Level Input Threshold
Low Level Input Threshold
S3, S5 Internal Pull-up Impedance to 5VSB
FAULT Output Impedance
TEMPERATURE MONITOR
Fault-Level Threshold (Note 6)
Shutdown-Level Threshold (Note 6)
NOTES:
2. Sleep-State Only for 3.3V Setting
3. Parameters not guaranteed for 5VSB < 4.0V.
4. At Ambient Temperatures Less Than 50°C.
5. Guaranteed by Correlation.
6. Guaranteed by Design.
125
-
-
155
-
-
°C
°C
FAULT = high
-
0.8
-
-
-
-
50
100
2.2
-
-
-
V
V
k
20
-
25
200
30
-
ms
s
I
5VDLSB
5VDLSB = 4V, 5VSB = 5V
-
-
-20
-
4.150
150
-
350
-
-
-40
-
V
mV
mA
I
VCLK
V
3V3
= 3.3V
V
VCLK
-
-
-
-
500
-
2.5
2.075
75
800
2.0
-
-
-
-
%
V
V
mV
mA
I
3V3DLSB
5VSB = 5V
V
3V3DL
-
-
-
-
5
-
-
3.3
2.739
99
10
90
2.0
-
-
-
-
-
%
V
V
mV
mA
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
(Continued)
SYMBOL
I
DRV2
TEST CONDITIONS
5VSB = 5V, R
SEL
= 1k
R
SEL
= 10k
MIN
220
-
TYP
-
200
MAX
-
-
UNITS
mA
FN4882 Rev 5.00
July 21, 2005
Page 5 of 14
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