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HIP6502
July 2000
File Number
4775.2
Multiple Linear Power Controller
with ACPI Control Interface
The HIP6502 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3V
DUAL
/3.3V
SB
voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply a choice of either or both of the computer system’s
2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5V
DUAL
plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
5V
DUAL
output is offered through the EN5VDL pin. In active
state, the 3.3V
DUAL
and 3.3V
MEM
linear regulators use
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors -
external to the controller on the 3.3V
DUAL
, internal on the
3.3V
MEM
. Active state regulation on the 2.5V
MEM
output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5V
DUAL
output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5V
DUAL
output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3V
DUAL
/3.3V
SB
output is active for as long as the ATX
5VSB voltage is applied to the chip. The 2.5V
CLK
output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
Features
• Provides 5 ACPI-Controlled Voltages
- 5V
DUAL
USB/Keyboard/Mouse (Active/Sleep)
- 3.3V
DUAL
/3.3V
SB
PCI/Auxiliary/LAN (Active/Sleep)
- 2.5V
MEM
RDRAM (Active/Sleep)
- 3.3V
MEM
SDRAM (Active/Sleep)
- 2.5V
CLK
Clock/Processor Terminations (Active Only)
• Excellent Output Voltage Regulation
- 3.3V
DUAL
/3.3V
SB
Output:
±2.0%
Over Temperature;
Sleep State Only
- 2.5V
MEM
and 3.3V
MEM
Output:
±2.0%
Over
Temperature; Both Operational States (3.3V
MEM
in
sleep only)
- 2.5V
CLK
Output:
±2.0%
Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6502
(SOIC)
TOP VIEW
VSEN2
1
20 MSEL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
5VSB 2
VSEN1 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL
S3
8
9
Ordering Information
PART NUMBER
HIP6502CB
HIP6502EVAL1
TEMP.
RANGE (
o
C)
0 to 70
PACKAGE
20 Ld SOIC
PKG.
NO.
M20.3
S5 10
Evaluation Board
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HIP6502
Absolute Maximum Ratings
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2 . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
12V
+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
Recommended Operating Conditions
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
±5%
Digital Inputs, V
SX
, V
EN5VDL
, V
MSEL
. . . . . . . . . . . . . . .0 to +5.25V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
Shutdown Supply Current
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
5VSB
I
5VSB(OFF)
V
SS
= 0.8V
-
-
30
14
-
-
mA
mA
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
Rising 5VSB POR Threshold
5VSB POR Hysteresis
Rising 12V Threshold
12V Hysteresis
Rising 3V3 and 5V Thresholds
3V3 and 5V Hysteresis
Soft-Start Current
Shutdown Voltage Threshold
3.3V
MEM
LINEAR REGULATOR (V
OUT1
)
Regulation
VSEN1 Nominal Voltage Level
VSEN1 Undervoltage Rising Threshold
VSEN1 Undervoltage Hysteresis
VSEN1 Output Current
2.5V
MEM
LINEAR REGULATOR (V
OUT2
)
Regulation
VSEN2 Nominal Voltage Level
VSEN2 Undervoltage Rising Threshold
VSEN2 Output Current
DRV2 Output Drive Current
I
VSEN2
I
DRV2
5VSB = 5V
5VSB = 5V
V
VSEN2
MSEL < 2.0V
-
-
-
250
220
-
2.5
2.075
300
-
2.0
-
-
-
-
%
V
V
mA
mA
I
VSEN1
5VSB = 5V
V
VSEN1
MSEL > 1.8V
-
-
-
-
250
-
3.3
2.77
110
300
2.0
-
-
-
-
%
V
V
mV
mA
I
SS
V
SD
-
-
-
-
-
-
-
-
-
0.2
-
1.0
90
5
10
-
4.5
-
10.2
-
-
-
-
0.8
V
V
V
V
%
%
µA
V
3.3V
DUAL
/3.3V
SB
LINEAR REGULATOR (V
OUT3
)
Sleep State Regulation
3V3DL Nominal Voltage Level
V
3V3DL
-
-
-
3.3
2.0
-
%
V
4-4
HIP6502
Electrical Specifications
PARAMETER
3V3DL Undervoltage Rising Threshold
3V3DL Undervoltage Hysteresis
3V3DLSB Output Drive Current
DLA Output Impedance
2.5V
CLK
LINEAR REGULATOR (V
OUT4
)
Regulation
VCLK Nominal Voltage Level
VCLK Undervoltage Rising Threshold
VCLK Undervoltage Hysteresis
VCLK Output Current (Note 2)
5V
DUAL
SWITCH CONTROLLER (V
OUT5
)
5VDL Undervoltage Rising Threshold
5VDL Undervoltage Hysteresis
5VDLSB Output Drive Current
5VDLSB Pull-Up Impedance to 5VSB
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 3)
Active-to-Sleep Control Input Delay
CONTROL I/O (S3, S5, EN5VDL, MSEL, FAULT)
High Level Input Threshold
Low Level Input Threshold
S3, S5 Internal Pull-up Impedance to 5VSB
FAULT Output Impedance
TEMPERATURE MONITOR
Fault-Level Threshold (Note 4)
Shutdown-Level Threshold (Note 4)
NOTES:
2. At Ambient Temperatures Less Than 50
o
C.
3. Guaranteed by Correlation.
4. Guaranteed by Design.
140
-
-
155
-
-
o
C
o
C
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
(Continued)
SYMBOL
TEST CONDITIONS
MIN
-
-
I
3V3DLSB
5VSB = 5V
5
-
TYP
2.77
110
8.5
90
MAX
-
-
-
-
UNITS
V
mV
mA
Ω
-
V
VCLK
-
-
-
I
VCLK
V
3V3
= 3.3V
500
-
2.5
2.10
80
800
2.0
-
-
-
-
%
V
V
mV
mA
-
-
I
5VDLSB
5VDLSB = 4V, 5VSB = 5V
-20
-
4.22
170
-
350
-
-
-40
-
V
mV
mA
Ω
20
-
25
200
30
-
ms
µs
-
0.8
-
FAULT = high
-
-
-
70
100
2.2
-
-
-
V
V
kΩ
Ω
4-5
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